 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| m68hc08 microcontrollers freescale.com mc68hc908gz60 mc68hc908gz48 mc68hc908gz32 data sheet mc68hc908gz60 rev. 6.0 04/2007
mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc., 20 05, 2006, 2007. all rights reserved. mc68hc908gz60 mc68hc908gz48 mc68hc908gz32 data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ revision history mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 4 freescale semiconductor the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) april, 2004 n/a initial release n/a may, 2004 1.0 9.7.3 keyboard interrupt polarity regi ster ? corrected the bit description of the kbip7?kbip0 bits. 119 14.8.8 esci prescaler register ? reworked note under pds2?pds0 description for clarity. 212 table 22-1. mc order numbers ? corrected order numbers. 329 figure 22-1. device numbering system ? reworked diagram to reflect correct order numbers. 329 table a-1. mc order numbers ? corrected order numbers. 342 figure a-3. device numbering system ? reworked diagram to reflect correct order numbers. 342 b.4 ordering information ? corrected order numbers. 346 figure b-3. device numbering system ? reworked diagram to reflect correct order numbers. 346 june, 2005 2.0 reformatted to freescale publication standards throughout table 14-6. esci lin control bits ? corrected functionality entries 211 14.9.1 esci arbiter control register ? corrected bit aclk bit description 215 14.9.3 bit time measurement ? corrected definition for aclk bit 216 march, 2006 3.0 10.5 clock generator module (cgm) ? updated description to remove erroneous information. 122 july, 2006 4.0 added section 1.5.15 unused pin termination 31 chapter 13 input/output (i/o) ports ? replaced note 169 table 14-6. esci lin control bits ? updated functionality column. 213 18.6 tim1 during break interrupts ? updated first paragraph for clarity. 270 19.6 tim2 during break interrupts ? updated first paragraph for clarity. 290 20.2.1.2 tim during break interrupts ? updated first paragraph for clarity. 302 figure 20-10. normal monitor mode circuit and figure 20-11. forced monitor mode ? changed capacitor values 307 21.5 5.0-vdc electrical characteri stics ? updated minimum value for low-voltage inhibit, trip rising voltage (vtripr). 317 21.9.2 cgm component information ? updated values for feedback bias resistor 322 mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 5 october, 2006 5.0 12.2 features ? corrected timer link connection from tim2 channel 0 to tim1 channel 0. 135 12.9 timer link ? corrected timer link connection from tim2 channel 0 to tim1 channel 0. 147 21.5 5.0-vdc electrical characteristics and 21.6 3.3-vdc electrical characteri stics ? updated dc injection current specification. 317 319 april, 2007 6.0 figure 2-2. control, status, and data registers ? changed tbmclksel to tmbclksel to be compatible with development tool nomenclature 37 chapter 5 configuration register (config) ? changed copclk to cgmxclk and tbmclksel to tmbc lksel to be compatible with development tool nomenclature 91 92 93 10.6.2 stop mode ? changed copclk to cgmxclk 125 figure 14-3. esci module block diagram ? changed bus_clk to bus clock and removed reference to 4xbusclk 192 14.4.2 transmitter ? changed escibdsrc to scibdsrc 194 14.9.1 esci arbiter control register and 14.9.3 bit time measurement ? replaced one quarter with one half in the definition for aclk = 1 217 218 figure 17-1. timebase block diagram , 17.5 tbm interrupt rate , and table 17-1. timebase divider selection ? changed tbmclksel to tmbclksel to be compatible with deve lopment tool nomenclature 260 261 21.9 clock generation module (cgm) characteristics ? updated section to include the following: 21.9.1 cgm operating conditions 21.9.2 cgm component information 21.9.3 cgm acquisition/lock time information 322 322 323 revision history (continued) date revision level description page number(s) revision history mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 6 freescale semiconductor mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 7 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 chapter 2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 chapter 3 analog-to-digital co nverter (adc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 chapter 4 clock generator module (cgm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 chapter 5 configuration regist er (config) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 chapter 6 computer operating properly (cop) module . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 chapter 7 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 chapter 8 external interrupt (i rq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 chapter 9 keyboard interrupt module (kbi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 chapter 10 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 chapter 11 low-voltage inhi bit (lvi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 chapter 12 mscan08 controller (mscan08). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 chapter 13 input/output (i/o) port s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 chapter 14 enhanced serial commun ications interface (esci) modu le . . . . . . . . . . . . . 189 chapter 15 system integration module (sim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 chapter 16 serial peripheral interface (spi) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 chapter 17 timebase module (tbm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 chapter 18 timer interface module (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 chapter 19 timer interface module (tim2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 chapter 20 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 chapter 21 electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 chapter 22 ordering information and mechanical specifications . . . . . . . . . . . . . . . . . . 333 appendix a mc68hc908gz48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 appendix b mc68hc908gz32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 list of chapters mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 8 freescale semiconductor mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 9 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.2.1 standard features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.2.2 features of the cpu08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.1 power supply pins (v dd and v ss ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.3 external reset pin (rst ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.5 cgm power supply pins (v dda and v ssa ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.6 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.7 adc power supply/reference pins (v ddad /v refh and v ssad /v refl ). . . . . . . . . . . . . . . . 29 1.5.8 port a input/output (i/o) pins (pta7/kbd7/ad15? pta0/kbd0/ad8) . . . . . . . . . . . . . . . . 30 1.5.9 port b i/o pins (ptb7/ad7?ptb0/ad0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.10 port c i/o pins (ptc6?ptc0/cantx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.11 port d i/o pins (ptd7/t2ch1?ptd0/ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.12 port e i/o pins (pte5?pte2, pte1/rxd, and pte0/t xd) . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.13 port f i/o pins (ptf7/t2ch5?ptf0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5.14 port g i/o pins (ptg7/ad23?ptbg0/ad16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5.15 unused pin termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 chapter 2 memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4 input/output (i/o) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6 flash-1 memory (flash-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.2 flash-1 control and block protect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.6.2.1 flash-1 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.6.2.2 flash-1 block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.6.3 flash-1 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.6.4 flash-1 mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.6.5 flash-1 page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table of contents mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 10 freescale semiconductor 2.6.6 flash-1 program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 2.6.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.6.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.6.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.7 flash-2 memory (flash-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.7.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.7.2 flash-2 control and block protect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.7.2.1 flash-2 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.7.2.2 flash-2 block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.7.3 flash-2 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.7.4 flash-2 mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.7.5 flash-2 page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.7.6 flash-2 program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 2.7.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.7.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.7.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 chapter 3 analog-to-digital converter (adc) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.3.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.3.4 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.3.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.3.6 result justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.4 monotonicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.7.1 adc analog power pin (v ddad ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.7.2 adc analog ground pin (v ssad ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.7.3 adc voltage reference high pin (v refh ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.7.4 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.7.5 adc voltage in (v adin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.8.1 adc status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.8.2 adc data register high and data register low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.8.2.1 left justified mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.8.2.2 right justified mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.8.2.3 left justified signed data mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 3.8.2.4 eight bit truncation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.8.3 adc clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 11 chapter 4 clock generator module (cgm) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.3.1 crystal oscillator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.3.2 phase-locked loop circuit (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.3.3 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.3.4 acquisition and tracking modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 4.3.5 manual and automatic pll bandwidth modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.3.6 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.3.7 special programming exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.3.8 base clock selector circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.3.9 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.4.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.4.3 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.4.4 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.4.5 pll analog ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.4.6 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.4.7 oscillator enable in stop mode bit (osceninstop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.4.8 crystal output frequency signal (cgmxclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.4.9 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.4.10 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.5.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 4.5.3 pll multiplier select register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.5.4 pll multiplier select register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 4.5.5 pll vco range select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.7 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.7.3 cgm during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.8 acquisition/lock time specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.8.1 acquisition/lock time definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.8.2 parametric influences on reaction time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.8.3 choosing a filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 chapter 5 configuration register (config) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table of contents mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 12 freescale semiconductor chapter 6 computer operating properly (cop) module 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.5 internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.6 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3.7 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.4 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.6 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.8 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 chapter 7 central processor unit (cpu) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 chapter 8 external interrupt (irq) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.4 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 13 8.6 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 13 chapter 9 keyboard interrupt module (kbi) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.4 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.6 keyboard module during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.7.1 keyboard status and control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.7.2 keyboard interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.7.3 keyboard interrupt polarity register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 chapter 10 low-power modes 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.1.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.1.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.2 analog-to-digital converter (adc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.2.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.2.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.3 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.3.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.3.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.4 central processor unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.4.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.4.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.5 clock generator module (cgm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.6 computer operating properly module (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.7 external interrupt module (irq). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.8 keyboard interrupt module (kbi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.9 low-voltage inhibit module (lvi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.9.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.9.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table of contents mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 14 freescale semiconductor 10.10 enhanced serial communications interface module (esci) . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.11 serial peripheral interface module (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.12 timer interface module (tim1 and tim2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.12.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.12.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.13 timebase module (tbm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.13.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.13.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.14 scalable controller area network module (mscan). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.14.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.14.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.15 exiting wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 10.16 exiting stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 chapter 11 low-voltage inhibit (lvi) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.3.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.3.2 forced reset operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.3.3 voltage hysteresis protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 11.3.4 lvi trip selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 11.4 lvi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 11.5 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 11.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 11.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 11.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 chapter 12 mscan08 controller (mscan08) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.3 external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.4 message storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.4.1 background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.4.2 receive structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.4.3 transmit structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.5 identifier acceptance filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.6.1 interrupt acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.6.2 interrupt vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 15 12.7 protocol violation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.8.1 mscan08 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.8.2 mscan08 soft reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.8.3 mscan08 power-down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.8.4 cpu wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.8.5 programmable wakeup function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.9 timer link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.10 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.11 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.12 programmer?s model of message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.12.1 message buffer outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 12.12.2 identifier registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.12.3 data length register (dlr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.12.4 data segment registers (dsrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.12.5 transmit buffer priority registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.13 programmer?s model of control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.13.1 mscan08 module control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.13.2 mscan08 module control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.13.3 mscan08 bus timing register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.13.4 mscan08 bus timing register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.13.5 mscan08 receiver flag register (crflg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.13.6 mscan08 receiver interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.13.7 mscan08 transmitter flag register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12.13.8 mscan08 transmitter control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.13.9 mscan08 identifier acceptance control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.13.10 mscan08 receive error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.13.11 mscan08 transmit error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 12.13.12 mscan08 identifier acceptance registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 12.13.13 mscan08 identifier mask registers (cidmr0?cidmr3). . . . . . . . . . . . . . . . . . . . . . . . . 167 chapter 13 input/output (i/o) ports 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 13.2 unused pin termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 13.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.3.3 port a input pullup enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 13.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.5 port c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 13.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 13.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 13.5.3 port c input pullup enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table of contents mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 16 freescale semiconductor 13.6 port d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.6.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.6.2 data direction register d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.6.3 port d input pullup enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 13.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 13.7.2 data direction register e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 13.8 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.8.1 port f data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.8.2 data direction register f. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.9 port g. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 13.9.1 port g data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 13.9.2 data direction register g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 chapter 14 enhanced serial communications interface (esci) module 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 14.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 14.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 14.4.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 14.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.4.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.4.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.4.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.4.2.4 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 14.4.2.5 inversion of transmitted output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 14.4.2.6 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 14.4.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 14.4.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.3.2 character reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.4.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.4.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.4.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 14.4.3.6 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.4.3.7 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.4.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.6 esci during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 03 14.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.7.1 pte0/txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.7.2 pte1/rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.8.1 esci control register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 14.8.2 esci control register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 17 14.8.3 esci control register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.8.4 esci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 14.8.5 esci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 14.8.6 esci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 14.8.7 esci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 14.8.8 esci prescaler register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 14.9 esci arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 14.9.1 esci arbiter control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 14.9.2 esci arbiter data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 14.9.3 bit time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 14.9.4 arbitration mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 chapter 15 system integrati on module (sim) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 15.2 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 15.2.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 15.2.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 15.2.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 15.3 reset and system initializat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 15.3.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 15.3.2 active resets from intern al sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 15.3.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.3.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.3.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15.3.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15.3.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 27 15.3.2.6 monitor mode entry module reset (modrst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15.4 sim counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 15.4.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 15.4.2 sim counter during stop mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 15.4.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 15.5 exception control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 15.5.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 15.5.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 15.5.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 15.5.1.3 interrupt status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 15.5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 15.5.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 15.5.4 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 15.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 15.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 15.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 15.7 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 15.7.1 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.7.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.7.3 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 table of contents mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 18 freescale semiconductor chapter 16 serial peripheral interface (spi) module 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16.3.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.3.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.4 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.4.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 16.4.2 transmission format when cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.4.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.4.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 16.5 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 16.6 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 16.6.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 16.6.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 16.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 16.8 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 16.9 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 16.9.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 16.9.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 16.10 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 16.11 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 16.11.1 miso (master in/slave out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 16.11.2 mosi (master out/slave in). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 16.11.3 spsck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 16.11.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 16.12 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 16.12.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 16.12.2 spi status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 16.12.3 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 chapter 17 timebase module (tbm) 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 17.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 17.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 17.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 17.5 tbm interrupt rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 17.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 17.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 17.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 17.7 timebase control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 19 chapter 18 timer interface module (tim1) 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 18.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 18.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 18.3.1 tim1 counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 18.3.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 18.3.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 18.3.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 18.3.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 67 18.3.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 18.3.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 18.3.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 18.3.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 18.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 18.5 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 18.6 tim1 during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 18.7 input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 18.8 input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 18.8.1 tim1 status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1 18.8.2 tim1 counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 18.8.3 tim1 counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 18.8.4 tim1 channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 18.8.5 tim1 channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 chapter 19 timer interface module (tim2) 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 19.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 19.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 19.3.1 tim2 counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 19.3.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 19.3.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 19.3.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 19.3.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 85 19.3.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 19.3.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 19.3.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 19.3.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 19.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 19.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 19.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 19.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 19.6 tim2 during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 table of contents mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 20 freescale semiconductor 19.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 19.7.1 tim2 clock pin (t2ch0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 19.7.2 tim2 channel i/o pins (t2ch5:t2ch2 and t2ch1:t 2ch0) . . . . . . . . . . . . . . . . . . . . . . 290 19.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 19.8.1 tim2 status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1 19.8.2 tim2 counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 19.8.3 tim2 counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 19.8.4 tim2 channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 19.8.5 tim2 channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 chapter 20 development support 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 20.2 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 20.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 20.2.1.1 flag protection during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 20.2.1.2 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 20.2.1.3 cop during break in terrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 02 20.2.2 break module registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 20.2.2.1 break status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 20.2.2.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 20.2.2.3 break status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 20.2.2.4 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 20.2.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 20.3 monitor module (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 20.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 20.3.1.1 normal monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 20.3.1.2 forced monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 20.3.1.3 monitor vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 20.3.1.4 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 20.3.1.5 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 20.3.1.6 baud rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 20.3.1.7 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 20.3.2 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 chapter 21 electrical specifications 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 21.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 21.3 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 21.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 21.5 5.0-vdc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 21.6 3.3-vdc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 21.7 5.0-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 21.8 3.3-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 21 21.9 clock generation module (cgm) charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 21.9.1 cgm operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 21.9.2 cgm component information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 21.9.3 cgm acquisition/lock time information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 21.10 5.0-volt adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 21.11 3.3-volt adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 21.12 5.0-volt spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 21.13 3.3-volt spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 21.14 timer interface module characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 21.15 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 chapter 22 ordering information and m echanical specifications 22.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 22.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 22.3 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 appendix a mc68hc908gz48 a.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 a.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 a.3 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 a.4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 appendix b mc68hc908gz32 b.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 b.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 b.3 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 b.4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 table of contents mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 22 freescale semiconductor mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 23 chapter 1 general description 1.1 introduction the mc68hc908gz60, mc68hc908gz48, and mc68hc908gz32 are members of the low-cost, high-performance m68hc08 family of 8-bit microcontroller units (mcus). all mcus in the family use the enhanced m68hc08 central processor unit (cpu08) and ar e available with a vari ety of modules, memory sizes and types, and package types. the information contained in this document pertains to all three devices with the exceptions noted in appendix a mc68hc908gz48 and appendix b mc68hc908gz32 . 1.2 features for convenience, features have been organized to reflect: ? standard features ? features of the cpu08 1.2.1 standard features features of the mc68hc908gz60 include: ? high-performance m68hc08 architecture optimized for c-compilers ? fully upward-compatible object code wi th m6805, m146805, and m68hc05 families ? 8-mhz internal bus frequency ? clock generation module supporting 1-mhz to 8-mhz crystals ? mscan08 (scalable controller area network) controller (implementing 2.0b protocol as defined in bosch specification dated september 1991) ? flash program memory security (1) ? on-chip programming firmware for use with hos t personal computer which does not require high voltage for entry ? in-system programming (isp) ? system protection features: ? optional computer operating properly (cop) reset ? low-voltage detection with optional reset and selectable trip points for 3.3-v and 5.0-v operation ? illegal opcode detection with reset ? illegal address detection with reset ? low-power design; fully static with stop and wait modes 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users. general description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 24 freescale semiconductor ? standard low-power modes of operation: ? wait mode ? stop mode ? master reset pin and power-on reset (por) ?on-chip flash memory: ? mc68hc908gz60 ? 60 kbytes ? mc68hc908gz48 ? 48 kbytes ? mc68hc908gz32 ? 32 kbytes ? random-access memory (ram): ? mc68hc908gz60 ? 2048 bytes ? mc68hc908gz48 ? 1536 bytes ? mc68hc908gz32 ? 1536 bytes ? serial peripheral interface (spi) module ? enhanced serial communicati ons interface (esci) module ? one 16-bit, 2-channel timer interfac e module (tim1) with selectable input capture, output compare, and pulse-width modulation (pwm) capability on each channel ? one 16-bit, 6-channel timer interfac e module (tim2) with selectable input capture, output compare, and pulse-width modulation (pwm) capability on each channel ? timebase module with clock prescaler circuitry for eight user selectable periodic real-time interrupts with optional active clock source durin g stop mode for periodic wakeup from stop using an external crystal ? 24-channel, 10-bit successive approximat ion analog-to-digital converter (adc) ? 8-bit keyboard wakeup port with software selectabl e rising or falling edge detect, as well as high or low level detection ? up to 53 general-purpose input/output (i/o) pins, including: ? 40 shared-function i/o pins, depending on package choice ? up to 13 dedicated i/o pins, depending on package choice ? selectable pullups on inputs only on ports a, c, and d. selection is on an i ndividual port bit basis. during output mode, pullups are disengaged. ? internal pullups on irq and rst to reduce customer system cost ? high current 10-ma sink/source capability on all port pins ? higher current 20-ma sink/source capability on ptc0?ptc4 and ptf0?ptf3 ? user selectable clockout feature with divide by 1, 2, and 4 of the bus or crystal frequency ? user selection of having the oscillator enabled or disabled during stop mode ? break module (brk) to allow single breakpoint setting during in-circuit debugging ? available packages: ? 32-pin low-profile quad flat pack (lqfp) ? 48-pin low-profile quad flat pack (lqfp) ? 64-pin quad flat pack (qfp) ? specific features in 32-pin lqfp are: ? port a is only 4 bits: pta0?pta3; shared with adc and kbi modules ? port b is only 6 bits: ptb0?ptb5; shared with adc module ? port c is only 2 bits: ptc0?ptc1; shared with mscan module ? port d is only 7 bits: ptd0?ptd6; shared with spi, tim1 and tim2 modules ? port e is only 2 bits: pte0?pte1; shared with esci module mcu block diagram mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 25 ? specific features in 48-pin lqfp are: ? port a is 8 bits: pta0?pta7; shared with adc and kbi modules ? port b is 8 bits: ptb0?ptb7; shared with adc module ? port c is only 7 bits: ptc0?ptc6; shared with mscan module ? port d is 8 bits: ptd0?ptd7; shared with spi, tim1, and tim2 modules ? port e is only 6 bits: pte0?pte5; shared with esci module ? specific features in 64-pin qfp are: ? port a is 8 bits: pta0?pta7; shared with adc and kbi modules ? port b is 8 bits: ptb0?ptb7; shared with adc module ? port c is only 7 bits: ptc0?ptc6; shared with mscan module ? port d is 8 bits: ptd0?ptd7; shared with spi, tim1, andtim2 modules ? port e is only 6 bits: pte0?pte5; shared with esci module ? port f is 8 bits: ptf0?ptf7; shared with tim2 module ? port g is 8 bits; ptg0?ptg 7; shared with adc module 1.2.2 features of the cpu08 features of the cpu08 include: ? enhanced hc05 programming model ? extensive loop control functions ? 16 addressing modes (eight more than the hc05) ? 16-bit index register and stack pointer ? memory-to-memory data transfers ? fast 8 8 multiply instruction ? fast 16/8 divide instruction ? binary-coded decimal (bcd) instructions ? optimization for controller applications ? efficient c language support 1.3 mcu block diagram figure 1-1 shows the structure of the mc68hc908gz60. refer to appendix a mc68hc908gz48 and appendix b mc68hc908gz32 . 1.4 pin assignments figure 1-2 , figure 1-3 , and figure 1-4 illustrate the pin assignments for the 32-pin lqfp, 48-pin lqfp, and 64-pin qfp respectively. general description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 26 freescale semiconductor figure 1-1. mc68hc908gz60 block diagram single breakpoint break module system integration module programmable timebase module monitor mode entry serial peripheral 6-channel timer interface module dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash ? 62,078 bytes user ram ? 2048 bytes monitor rom user flash vector space ? 52 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 rst (1) irq (1) interface module interrupt module computer operating properly module pta7/kbd7/ad15? 10-bit analog-to-digital converter module ptc6 (2) ptc5 (2) ptc4 (2, 3) ptc3 (2, 3) ptc2 (2, 3) ptc1/can rx (2, 3) ptc0/can tx (2, 3) ptd7/t2ch1 (2) ptd6/t2ch0 (2) ptd5/t1ch1 (2) ptd4/t1ch0 (2) ptd3/spsck (2) ptd2/mosi (2) ptd1/miso (2) ptd0/ss /mclk (2) pte1/rxd pte0/txd 2-channel timer interface module enhanced serial interface module security module power-on reset module memory map module configuration register 1?2 module power v ss v dd v ssa v dda 1. pin contains in tegrated pullup device. 2. ports are software configurable with pullup device if input port or pullup/pulldow n device for keyboard input. 3. higher current drive port pins v ddad /v refh v ssad /v refl pte5?pte2 communications clock generator module cgmxfc phase locked loop 1?8 mhz oscillator portb ddrb ptb7/ad7? portf ddrf ptf7/t2ch5 module portg ddrg ptg7/ad23? ptf6/t2ch4 ptf5/t2ch3 ptf4/t2ch2 ptf3?pft0 (3) mscan module pta0/kbd0/ad8 (2) ptb0/ad0 ptg0/ad16 pin assignments mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 27 figure 1-2. 32-pin lqfp pin assignments figure 1-3. 48-pin lqfp pin assignments ptd3/spsck pta3/kbd3/ad1 ptd2/mosi ptd1/miso ptd0/ss /mclk irq pte1/rxd pte0/txd rst pta2/kbd2/ad10 pta1/kbd1/ad9 pta0/kbd0/ad8 v ssad /v refl v ddad /v refh ptb5/ad5 ptb4/ad4 ptb3/ad3 osc1 osc2 cgmxfc v ssa v dda ptc1/can rx ptc0/can tx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 ptb2/ad2 v ss v dd ptd4/t1ch0 ptd5/t1ch1 ptd6/t2ch0 ptb0/ad0 ptb1/ad1 36 37 13 rst ptd0/ss /mclk ptd1/miso ptd2/mosi pte0/txd pte1/rxd pte2 pte3 pte4 pte5 irq ptc3 ptc2 ptd7/t2ch1 ptd6/t2ch0 ptd5/t1ch1 ptd4/t1ch0 v dd v ss ptc4 ptb0/ad0 ptb1/ad1 pta5/kbd5/ad13 pta6/kbd6/ad14 ptc1/can rx cgmxfc v ssa v dda pta7/kbd7/ad15 ptc0/can tx pta4/kbd4/ad12 pta3/kbd3/ad11 osc2 12 24 25 v ddad /v refh v ssad /v refl ptc5 ptc6 pta0/kbd0/ad8 ptb4/ad4 ptb5/ad5 ptb3/ad3 ptb6/ad6 ptb7/ad7 pta1/kbd1/ad9 pta2/kbd2/ad10 ptb2/ad2 ptd3/spsck 48 osc1 46 45 44 43 42 41 40 39 38 1 2 3 4 5 6 7 8 9 10 14 15 16 17 18 19 20 21 22 11 23 35 34 33 32 31 30 29 28 27 26 47 general description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 28 freescale semiconductor figure 1-4. 64-pin qfp pin assignments 1.5 pin functions descriptions of the pin functions are provided here. 1.5.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. th e mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu as figure 1-5 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response ceramic capacitor for c1. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. pte4 1 pte1/rxd pte2 pte5 ptf0 ptf1 ptf2 ptf6/t2ch4 ptf5/t2ch3 ptf4/t2ch2 ptd7/t2ch1 ptd6/t2ch0 ptd5/t1ch1 ptd4/t1ch0 ptg1/ad17 ptg2/ad18 ptg3/ad19 ptc5 ptc6 ptb5/ad5 ptg0/ad16 pta5/kbd5/ad13 ptg4/ad20 osc1 ptg7/ad23 ptg6/ad22 ptg5/ad21 pta2/kbd2/ad10 pta6/kbd6/ad14 pta7/kbd7/ad15 17 32 33 49 48 64 ptf3 irq ptd0/ss /mclk 16 ptd3/spsck ptf7/t2ch5 ptc2 ptc3 ptc4 v ssad /v refl v ddad /v refh ptb7/ad7 ptb6/ad6 ptc0/can tx ptc1/can rx v dda v ssa pte3 ptd1/miso ptd2/mosi ptb0/ad0 pta0/kbd0/ad8 pta1/kbd1/ad9 osc2 cgmxfc rst pte0/txd v ss v dd ptb1/ad1 ptb2/ad2 ptb4/ad4 ptb3/ad3 pta4/kbd4/ad12 pta3/kbd3/ad11 2 3 4 5 6 7 8 43 42 41 40 39 38 18 19 20 21 22 23 50 51 52 53 54 55 9 10 11 24 25 26 27 37 36 35 34 56 57 58 59 12 13 14 15 28 29 30 31 44 45 46 47 63 62 61 60 pin functions mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 29 figure 1-5. power supply bypassing 1.5.2 oscillator pins (osc1 and osc2) osc1 and osc2 are the connections for an exter nal crystal, resonator, or clock circuit. see chapter 4 clock generator module (cgm) . 1.5.3 external reset pin (rst ) a low on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal re set source is asserted. this pin contains an internal pullup resistor. see chapter 15 system integration module (sim). 1.5.4 external interrupt pin (irq ) irq is an asynchronous external interrupt pin. th is pin contains an internal pullup resistor. see chapter 8 external interrupt (irq). 1.5.5 cgm power supply pins (v dda and v ssa ) v dda and v ssa are the power supply pins for the analog portion of the clock generator module (cgm). decoupling of these pins should be as per the digital supply. see chapter 4 clock generator module (cgm) . 1.5.6 external filter capacitor pin (cgmxfc) cgmxfc is an external filter c apacitor connection for the cgm. see chapter 4 clock generator module (cgm) . 1.5.7 adc power supply/reference pins (v ddad /v refh and v ssad /v refl ) v ddad and v ssad are the power supply pins to the analog-to-digital converter (adc). v refh and v refl are the reference voltage pins for the adc. v refh is the high reference supply for the adc, and by default the v ddad /v refh pin should be externally filtered and connec ted to the same voltage potential as v dd . mcu v dd c2 c1 0.1 f v ss v dd + note: component values shown represent typical applications. general description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 30 freescale semiconductor v refl is the low reference supply for the adc, and by default the v ssad /v refl pin should be connected to the same voltage potential as v ss . see chapter 3 analog-to-digital converter (adc) . 1.5.8 port a input/output (i/o ) pins (pta7/kbd7/ad 15?pta0/kbd0/ad8) pta7?pta0 are general-purpose, bidirectional i/o port pins. any or all of the port a pins can be programmed to serve as keyboard interrupt pins or used as analog-to-digital inputs. pta7?pta4 are only available on the 48-pin lqfp and 64-pin qfp packages. see chapter 13 input/output (i/o) ports , chapter 9 keyboard interrupt module (kbi) , and chapter 3 analog-to-digital converter (adc) . these port pins also have selectable pullups when configured for input mode. the pullups are disengaged when configured for output mode. the pullups are selectable on an individual port bit basis. 1.5.9 port b i/o pi ns (ptb7/ad7?ptb0/ad0) ptb7?ptb0 are general-purpose, bidirectional i/o por t pins that can also be used for analog-to-digital converter (adc) inputs. ptb7?ptb6 are only avai lable on the 48-pin lqfp and 64-pin qfp packages. see chapter 13 input/output (i/o) ports and chapter 3 analog-to-digital converter (adc) . 1.5.10 port c i /o pins (ptc6?ptc0/can tx ) ptc6 and ptc5 are general-purpose , bidirectional i/o port pins. ptc4?ptc0 are general-purpose, bidirectional i/o por t pins that contain higher current sink/source capability. ptc6?ptc2 are only available on the 48-pin lqfp and 64-pin qfp packages. see chapter 13 input/output (i/o) ports . ptc1 and ptc0 can be programmed to be mscan08 pins. these port pins also have selectable pullups when configured for input mode. the pullups are disengaged when configured for output mode. the pullups are selectable on an individual port bit basis. 1.5.11 port d i/o pins (ptd7/t2ch1?ptd0/ss ) ptd7?ptd0 are special-function, bidirectional i/o port pins. ptd3?ptd0 can be programmed to be serial peripheral interface (spi) pins, while ptd7?ptd4 can be indi vidually programmed to be timer interface module (tim1 and tim2) pins. ptd0 can be used to output a clock, mclk. ptd7 is only available on the 48-pin lqfp and 64-pin qfp packages. see chapter 18 timer interface module (tim1) , chapter 19 timer interface module (tim2) , chapter 16 serial peripheral interface (spi) module , chapter 13 input/output (i/o) ports . and chapter 5 configuration register (config) . these port pins also have selectable pullups when configured for input mode. the pullups are disengaged when configured for output mode. the pullups are selectable on an individual port bit basis. 1.5.12 port e i/o pins (pte5? pte2, pte1/rxd, and pte0/txd) pte5?pte0 are general-purpose, bidirectional i/o port pins. pte1 and pte0 can also be programmed to be enhanced serial communications interface (esci) pins. pte5?pte2 are only available on the 48-pin lqfp and 64-pin qfp packages. see chapter 14 enhanced serial communications interface (esci) module and chapter 13 input/output (i/o) ports . pin functions mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 31 1.5.13 port f i/ o pins (ptf7/t2ch5?ptf0) ptf7?ptf4 are special-function, bi directional i/o port pins that c an be individually programmed to be timer interface module (tim2) pins. ptf3?ptf0 are general-purpose, bidirectional i/o port pins that contain higher current sink/source capability. ptf7?ptf0 are only available on the 64-pin qfp package. see chapter 18 timer interface module (tim1), chapter 19 timer interface module (tim2), and chapter 13 input/output (i/o) ports . 1.5.14 port g i/o pins (ptg7/ad23?ptbg0/ad16) ptg7?ptg0 are general-purpose, bidirectional i/o port pins that can also be used for analog-to-digital converter (adc) inputs. ptg7?ptg0 are only available on the 64-pin qfp package. see chapter 13 input/output (i/o) ports and chapter 3 analog-to-digital converter (adc) . 1.5.15 unused pin termination input pins and i/o port pins that are not used in t he application must be terminated. this prevents excess current caused by floating inputs, and enhances immu nity during noise or transient events. termination methods include: 1. configuring unused pins as outputs and driving high or low; 2. configuring unused pins as i nputs and enabling internal pull-ups; 3. configuring unused pins as inputs and us ing external pull-up or pull-down resistors. never connect unused pins directly to v dd or v ss . since some general-purpose i/o pins are not available on all packages, these pins must be terminated as well. either method 1 or 2 above are appropriate. general description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 32 freescale semiconductor mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 33 chapter 2 memory 2.1 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: ? 62,078 bytes of user flash memory ? 2048 bytes of random-access memory (ram) ? 52 bytes of user-defined vectors 2.2 unimplemented memory locations accessing an unimplemented location can cause an illegal address reset. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded. 2.3 reserved memory locations accessing a reserved location can have unpredictable effects on microcontroller (mcu) operation. in the figure 2-1 and in register figures in this document, rese rved locations are marked with the word reserved or with the letter r. 2.4 input/output (i/o) section most of the control, status, and data registers are in the zero page area of $0000?$003f, or at $0440?$0461. additional i/o registers have these addresses: ? $fe00; sim break status register, bsr ? $fe01; sim reset status register, srsr ? $fe02; reserved ? $fe03; sim break flag control register, bfcr ? $fe04; interrupt status register 1, int1 ? $fe05; interrupt status register 2, int2 ? $fe06; interrupt status register 3, int3 ? $fe07; interrupt status register 4, int4 ? $fe08; flash-2 control register, fl2cr ? $fe09; break address register high, brkh ? $fe0a; break address register low, brkl ? $fe0b; break status and control register, brkscr ? $fe0c; lvi status register, lvisr ? $fe0d; flash-2 test control register, fltcr2 ? $fe0e; flash-1 test control register, fltcr1 ? $ff80; flash-1 block protect register, fl1bpr memory mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 34 freescale semiconductor ? $ff81; flash-2 block protect register, fl2bpr ? $ff88; flash-1 control register, fl1cr data registers are shown in figure 2-2 . table 2-1 is a list of vector locations. $0000 $003f i/o registers 64 bytes $fe00 sim break status register (bsr) $fe01 sim reset status register (srsr) $fe02 reserved $0040 $043f ram-1 1024 bytes $fe03 sim break flag control register (bfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $0440 $0461 i/o registers 34 bytes $fe06 interrupt status register 3 (int3) $fe07 interrupt status register 4 (int4) $fe08 flash-2 control register (fl2cr) $0462 $04ff flash-2 158 bytes $fe09 break address register high (brkh) $fe0a break address register low (brkl) $fe0b break status and co ntrol register (brkscr) $0500 $057f mscan control and message buffer 128 bytes $fe0c lvi status register (lvisr) $fe0d flash-2 test control register (fltcr2) $fe0e flash-1 test control register (fltcr1) $0580 $097f ram-2 1024 bytes $fe0f unimplemented $fe10 $fe1f unimplemented 16 bytes reserved for compatibility with monitor code for a-family part $0980 $1b7f flash-2 4608 bytes $fe20 $ff7f monitor rom 352 bytes $1b80 $1dff reserved 640 bytes $ff80 flash-1 block prot ect register (fl1bpr) $ff81 flash-2 block prot ect register (fl2bpr) $1e00 $1e0f monitor rom 16 bytes $ff82 $ff87 reserved 6 bytes $1e10 $1e1f reserved 16 bytes $ff88 flash-1 control register (fl1cr) $1e20 $7fff flash-2 25,056 bytes $ff89 $ffcb reserved 67 bytes $8000 $fdff flash-1 32,256 bytes $ffcc $ffff (1) flash-1 vectors 52 bytes 1. $fff6?$fffd used for eight security bytes figure 2-1. mc68hc908gz60 memory map input/output (i/o) section mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 35 addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 173. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 176. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 178. read: 1 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) see page 180. read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) see page 174. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 176. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) see page 178. read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) see page 181. read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) see page 183. read: 0 0 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 esci prescaler register (scpsc) see page 214. read: pds2 pds1 pds0 pssb4 pssb3 pssb2 pssb1 pssb0 write: reset:00000000 $000a esci arbiter control register (sciactl) see page 217. read: am1 alost am0 aclk afin arun arovfl ard8 write: reset:00000000 $000b esci arbiter data register (sciadat) see page 218. read: ard7 ard6 ard5 ar d4 ard3 ard2 ard1 ard0 write: reset:00000000 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 1 of 9) memory mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 36 freescale semiconductor $000c data direction register e (ddre) see page 184. read: 0 0 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 $000d port a input pullup enable register (ptapue) see page 175. read: ptapue7 ptapue6 ptapue5 ptapu e4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000e port c input pullup enable register (ptcpue) see page 180. read: 0 ptcpue6 ptcpue5 ptcpue4 ptcpue3 ptcpue2 ptcpue1 ptcpue0 write: reset:00000000 $000f port d input pullup enable register (ptdpue) see page 182. read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset:00000000 $0010 spi control register (spcr) see page 255. read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $0011 spi status and control register (spscr) see page 256. read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 $0012 spi data register (spdr) see page 258. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0013 esci control register 1 (scc1) see page 204. read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0014 esci control register 2 (scc2) see page 206. read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 esci control register 3 (scc3) see page 208. read: r8 t8 r r orie neie feie peie write: reset:u0000000 $0016 esci status register 1 (scs1) see page 209. read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 esci status register 2 (scs2) see page 211. read: 000000bkfrpf write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 2 of 9) input/output (i/o) section mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 37 $0018 esci data register (scdr) see page 212. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 esci baud rate register (scbr) see page 212. read: lint linr scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 $001a keyboard status and control register (intkbscr) see page 120. read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (intkbier) see page 121. read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $001c timebase module control register (tbcr) see page 262. read: tbif tbr2 tbr1 tbr0 0 tbie tbon r write: tack reset:00000000 $001d irq status and control register (intscr) see page 114. read: 0000irqf0 imask mode write: ack reset:00000000 $001e configuration register 2 (config2) (1) see page 92. read: 0 mclksel mclk1 mclk0 mscan- en (1) tmbclk- sel oscenin- stop scibdsrc write: reset:00000001 $001f configuration register 1 (config1) (1) see page 93. read: coprs lvistop lvirstd lvipwrd lvi5or3 (1) ssrec stop copd write: reset:00000000 1. one-time writable register after each reset, except mscanen and lvi5or3 bits. mscanen andlvi5or3 bits are only reset via por (power-on reset). $0020 tim1 status and control register (t1sc) see page 271. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 tim1 counter register high (t1cnth) see page 273. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 tim1 counter register low (t1cntl) see page 273. read: bit 7 654321bit 0 write: reset:00000000 $0023 tim1 counter modulo register high (t1modh) see page 273. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 3 of 9) memory mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 38 freescale semiconductor $0024 tim1 counter modulo register low (t1modl) see page 273. read: bit 7654321bit 0 write: reset:11111111 $0025 tim1 channel 0 status and control register (t1sc0) see page 274. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 tim1 channel 0 register high (t1ch0h) see page 277. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0027 tim1 channel 0 register low (t1ch0l) see page 277. read: bit 7654321bit 0 write: reset: indeterminate after reset $0028 tim1 channel 1 status and control register (t1sc1) see page 274. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 tim1 channel 1 register high (t1ch1h) see page 277. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002a tim1 channel 1 register low (t1ch1l) see page 277. read: bit 7654321bit 0 write: reset: indeterminate after reset $002b tim2 status and control register (t2sc) see page 291. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $002c tim2 counter register high (t2cnth) see page 292. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $002d tim2 counter register low (t2cntl) see page 292. read: bit 7 654321bit 0 write: reset:00000000 $002e tim2 counter modulo register high (t2modh) see page 293. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $002f tim2 counter modulo register low (t2modl) see page 293. read: bit 7654321bit 0 write: reset:11111111 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 4 of 9) input/output (i/o) section mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 39 $0030 tim2 channel 0 status and control register (t2sc0) see page 293. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0031 tim2 channel 0 register high (t2ch0h) see page 297. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0032 tim2 channel 0 register low (t2ch0l) see page 297. read: bit 7654321bit 0 write: reset: indeterminate after reset $0033 tim2 channel 1 status and control register (t2sc1) see page 293. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0034 tim2 channel 1 register high (t2ch1h) see page 297. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0035 tim2 channel 1 register low (t2ch1l) see page 297. read: bit 7654321bit 0 write: reset: indeterminate after reset $0036 pll control register (pctl) see page 83. read: pllie pllf pllon bcs r r vpr1 vpr0 write: reset:00100000 $0037 pll bandwidth control register (pbwc) see page 85. read: auto lock acq 0000 r write: reset:00000000 $0038 pll multiplier select high register (pmsh) see page 86. read: 0000 mul11 mul10 mul9 mul8 write: reset:00000000 $0039 pll multiplier select low register (pmsl) see page 86. read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 $003a pll vco select range register (pmrs) see page 87. read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 $003b reserved read: 0000 rrrr write: reset:00000001 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 5 of 9) memory mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 40 freescale semiconductor $003c adc status and control register (adscr) see page 68. read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: r reset:00011111 $003d adc data high register (adrh) see page 70. read: 000000ad9ad8 write: reset: unaffected by reset $003e adc data low register (adrl) see page 70. read: ad7 ad6 ad5 ad4 a3 ad2 ad1 ad0 write: reset: unaffected by reset $003f adc clock register (adclk) see page 72. read: adiv2 adiv1 adiv0 adiclk mode1 mode0 r 0 write: reset:00000100 $0440 port f data register (ptf) see page 185. read: ptf7 ptf6 ptf5 ptf4 ptaf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset $0441 port g data register (ptg) see page 186. read: ptg7 ptg6 ptg5 ptg4 ptg3 ptg2 ptg1 ptg0 write: reset: unaffected by reset $0444 data direction register f (ddrf) see page 185. read: ddrf7 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset:00000000 $0445 data direction register g (ddrg) see page 187. read: ddrg7 ddrg6 ddrg5 ddrg4 ddrg3 ddrg2 ddrg1 ddrg0 write: reset:00000000 $0448 keyboard interrupt polarity register (intkbipr) see page 121. read: kbip7 kbip6 kbip5 kbip4 kbip3 kbip2 kbip1 kbip0 write: reset:00000000 $0456 tim2 channel 2 status and control register (t2sc2) see page 297. read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 $0457 tim2 channel 2 register high (t2ch2h) see page 297. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0458 tim2 channel 2 register low (t2ch2l) see page 297. read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 6 of 9) input/output (i/o) section mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 41 $0459 tim2 channel 3 status and control register (t2sc3) see page 293. read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 $045a tim2 channel 3 register high (t2ch3h) see page 297. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $045b tim2 channel 3 register low (t2ch3l) see page 297. read: bit 765432 1bit 0 write: reset: indeterminate after reset $045c tim2 channel 4 status and control register (t2sc4) see page 293. read: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max write: 0 reset:00000000 $045d tim2 channel 4 register high (t2ch4h) see page 297. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $045e tim2 channel 4 register low (t2ch4l) see page 297. read: bit 7654321 bit 0 write: reset: indeterminate after reset $045f tim2 channel 5 status and control register (t2sc5) see page 293. read: ch5f ch5ie 0 ms5a els5b els5a tov 5 ch5max write: 0 reset:00000000 $0460 tim2 channel 5 register high (t2ch5h) see page 297. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0461 tim2 channel 5 register low (t2ch5l) see page 297. read: bit 7654321 bit 0 write: reset: indeterminate after reset $fe00 break status register (bsr) see page 237. read: rrrrrr sbsw r write: note 1 reset:00000000 1. writing a 0 clears sbsw. $fe01 sim reset status register (srsr) see page 237. read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 7 of 9) memory mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 42 freescale semiconductor $fe03 break flag control register (bfcr) see page 238. read: bcferrrrrrr write: reset:00000000 $fe04 interrupt status register 1 (int1) see page 231. read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) see page 233. read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) see page 233. read: if22 if21 if20 if19 if18 if17 if16 if15 write:rrrrrrrr reset:00000000 $fe07 interrupt status register 4 (int4) see page 233. read: 000000if24if23 write:rrrrrrrr reset:00000000 $fe08 flash-2 control register (fl2cr) see page 53. read: 0000 hven mass erase pgm write: reset:00000000 $fe09 break address register high (brkh) see page 303. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0a break address register low (brkl) see page 303. read: bit 7654321bit 0 write: reset:00000000 $fe0b break status and control register (brkscr) see page 303. read: brke brka 000000 write: reset:00000000 $fe0c lvi status register (lvisr) see page 133. read: lviout 0000000 write: reset:00000000 $fe0d flash-2 test control register (fltcr2) read: rrrrrrrr write: reset:00000000 $fe0e flash-1 test control register (fltcr1) read: rrrrrrrr write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 8 of 9) input/output (i/o) section mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 43 . $ff80 flash-1 block protect register (fl1bpr) (1) see page 47. read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset $ff81 flash-2 block protect register (fl2bpr) (1) see page 54. read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset 1. non-volatile flash register $ff88 flash-1 control register (fl1cr) see page 46. read: 0000 hven mass erase pgm write: reset:00000000 $ffff cop control register (copctl) see page 97. read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset table 2-1. vector addresses vector priority ve ctor address vector lowest if24 $ffcc tim2 channel 5 vector (high) $ffcd tim2 channel 5 vector (low) if23 $ffce tim2 channel 4 vector (high) $ffcf tim2 channel 4 vector (low) if22 $ffd0 tim2 channel 3 vector (high) $ffd1 tim2 channel 3 vector (low) if21 $ffd2 tim2 channel 2 vector (high) $ffd3 tim2 channel 2 vector (low) if20 $ffd4 mscan08 transmit vector (high) $ffd5 mscan08 transmit vector (low) if19 $ffd6 mscan08 receive vector (high) $ffd7 mscan08 receive vector (low) if18 $ffd8 mscan08 error vector (high) $ffd9 mscan08 error vector (low) if17 $ffda mscan08 wakeup vector (high) $ffdb mscan08 wakeup vector (low) if16 $ffdc timebase vector (high) $ffdd timebase vector (low) addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 9 of 9) memory mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 44 freescale semiconductor highest if15 $ffde adc conversion complete vector (high) $ffdf adc conversion complete vector (low) if14 $ffe0 keyboard vector (high) $ffe1 keyboard vector (low) if13 $ffe2 esci transmit vector (high) $ffe3 esci transmit vector (low) if12 $ffe4 esci receive vector (high) $ffe5 esci receive vector (low) if11 $ffe6 esci error vector (high) $ffe7 esci error vector (low) if10 $ffe8 spi transmit vector (high) $ffe9 spi transmit vector (low) if9 $ffea spi receive vector (high) $ffeb spi receive vector (low) if8 $ffec tim2 overflow vector (high) $ffed tim2 overflow vector (low) if7 $ffee tim2 channel 1 vector (high) $ffef tim2 channel 1 vector (low) if6 $fff0 tim2 channel 0 vector (high) $fff1 tim2 channel 0 vector (low) if5 $fff2 tim1 overflow vector (high) $fff3 tim1 overflow vector (low) if4 $fff4 tim1 channel 1 vector (high) $fff5 tim1 channel 1 vector (low) if3 $fff6 tim1 channel 0 vector (high) $fff7 tim1 channel 0 vector (low) if2 $fff8 pll vector (high) $fff9 pll vector (low) if1 $fffa irq vector (high) $fffb irq vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) $ffff reset vector (low) table 2-1. vector addresses (continued) vector priority ve ctor address vector random-access memory (ram) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 45 2.5 random-access memory (ram) the ram locations are broken into two non-contin uous memory blocks. the ram addresses locations are $0040?$043f and $0580?$097f. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. note for correct operation, the stack pointer must point only to ram locations. within page zero are 192 bytes of ram. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and us er data or code. when the stack pointer is moved from its reset location at $00ff out of page zero, direct addressing mode instru ctions can efficiently access all page zero ram locations. page zero ram, therefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note for m6805 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note be careful when using nested subrouti nes. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. 2.6 flash-1 memory (flash-1) this subsection describes the operation of the emb edded flash-1 memory. this memory can be read, programmed, and erased from a single external su pply. the program and erase operations are enabled through the use of an internal charge pump. 2.6.1 functional description the flash-1 memory is an array of 32,256 bytes with two bytes of block protection (one byte for protecting areas within flash-1 array and one byte for protecting areas within flash-2 array) and an additional 52 bytes of user vectors. an erased bi t reads as a 1 and a programmed bit reads as a 0. memory in the flash-1 array is organized into rows within pages. there are two rows of memory per page with 64 bytes per row. the minimum erase bl ock size is a single page, 128 bytes. programming is performed on a per-row basis, 64 bytes at a time. pr ogram and erase operations are facilitated through control bits in the flash-1 control register (fl1cr) . details for these operations appear later in this subsection. the flash-1 memory map consists of: ? $8000?$fdff: user memory (32,256 bytes) ? $ff80: flash-1 block protect register (fl1bpr) ? $ff81: flash-2 block protect register (fl2bpr) ? $ff88: flash-1 control register (fl1cr) ? $ffcc?$ffff: these locations are reserved for user-defined interrupt and reset vectors (see table 2-1 for details) memory mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 46 freescale semiconductor programming tools are available from freescale. cont act your local freescale representative for more information. note a security feature prevents viewing of the flash contents. (1) 2.6.2 flash-1 control an d block protect registers the flash-1 array has two registers that control its operation, the flash-1 control register (fl1cr) and the flash-1 block protect register (fl1bpr). 2.6.2.1 flash-1 control register the flash-1 control register (fl1cr) controls flash program and erase operations. hven ? high-voltage enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operations in the array. hven can only be set if either pgm = 1 or erase = 1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit setting this read/write bit configures t he flash-1 array for mass erase operation. 1 = mass erase operation selected 0 = mass erase operation unselected erase ? erase control bit this read/write bit configures t he memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures the memory for progr am operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users. address: $ff88 bit 7654321bit 0 read:0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 2-3. flash-1 control register (fl1cr) flash-1 memory (flash-1) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 47 2.6.2.2 flash-1 block protect register the flash-1 block protect register (fl1bpr) is im plemented as a byte within the flash-1 memory; therefore, it can only be written during a flash pr ogramming sequence. the value in this register determines the starting location of the protected range within the flash-1 memory. fl1bpr[7:0] ? block protect register bits 7 to 0 these eight bits represent bits [14:7] of a 16-bit memory address. bit 15 is a 1 and bits [6:0] are 0s. the resultant 16-bit address is used for specifying the start address of the flash-1 memory for block protection. flash-1 is protected from this start address to the end of flash-1 memory at $ffff. with this mechanism, the protect start addres s can be $xx00 and $xx80 (128 byte page boundaries) within the flash-1 array. figure 2-5. flash-1 block protect start address decreasing the value in fl1bpr by one increa ses the protected range by one page (128 bytes). however, programming the block protect register with $fe protects a range twice that size, 256 bytes, in the corresponding array. $fe means that locations $ff00?$ffff are protected in flash-1. the flash memory does not exist at some location s. the block protection range configuration is unaffected if flash memory does not exist in that range. refer to figure 2-1 and make sure that the desired locations are protected. address: $ff80 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: unaffected by reset figure 2-4. flash-1 block protect register (fl1bpr) table 2-2. flash-1 protected ranges fl1bpr[7:0] protected range $ff no protection $fe $ff00?$ffff $fd $0b $fe80?$ffff $8580?$ffff $0a $8500?$ffff $09 $8480?$ffff $08 $04 $8400?$ffff $8200?$ffff $03 $8180?$ffff $02 $8100?$ffff $01 $8080?$ffff $00 $8000?$ffff 1 flbpr value 16-bit memory address 0000000 start address of flash block protect memory mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 48 freescale semiconductor 2.6.3 flash-1 block protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made fo r protecting blocks of memory from unintentional erase or program operations due to system malfunction. this protec tion is done by using the flash-1 block protection register (fl1bpr). fl1bpr determines the range of the flash-1 memory which is to be protected. the range of the protected area starts from a locati on defined by fl1bpr and ends at the bottom of the flash-1 memory ($ffff). when the memory is protected, the hven bit can not be set in either erase or program operations. note in performing a program or erase operation, the flash-1 block protect register must be read after setting the pgm or erase bit and before asserting the hven bit. when the flash-1 block protect register is programmed with all 0?s, the entire memory is protected from being programmed and erased. when all the bits are erased (all 1?s), the entire memory is accessible for program and erase. when bits within fl1bpr are programmed (0), they lock a block of memory address ranges as shown in figure 2-4 . if fl1bpr is programmed with any value other than $ff, the protected block of flash memory can not be erased or programmed. note the vector locations and the flash block protect registers are located in the same page. fl1bpr and fl2bpr are not protected with special hardware or software. therefore, if this page is not protected by fl1bpr and the vector locations are erased by either a page or a mass erase operation, then both fl1bpr and fl2bpr will also get erased. 2.6.4 flash-1 mass erase operation use this step-by-step procedure to erase the entire flash-1 memory: 1. set both the erase bit and the mass bit in the flash-1 control register (fl1cr). 2. read the flash-1 block protect register (fl1bpr). note mass erase is disabled whenever any bl ock is protected (fl1bpr does not equal $ff). 3. write to any flash-1 address within the flash-1 array with any data. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t merase (minimum 4 ms). 7. clear the erase and mass bits. 8. wait for a time, t nvhl (minimum 100 s). 9. clear the hven bit. 10. wait for a time, t rcv , (typically 1 s) after which the memory can be accessed in normal read mode. notes a. programming and erasing of flash locations can not be performed by code being executed from the same flash array. flash-1 memory (flash-1) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 49 b. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. however, care must be taken to ensure that these operations do not access any address within the flash array memory space such as the cop control register (copctl) at $ffff. c. it is highly recommended that interrupts be disabled during program/erase operations. 2.6.5 flash-1 pa ge erase operation use this step-by-step procedure to erase a page (128 bytes) of flash-1 memory: 1. set the erase bit and clear the mass bit in the flash-1 control register (fl1cr). 2. read the flash-1 block protect register (fl1bpr). 3. write any data to any flash-1 address within the address range of the page (128 byte block) to be erased. 4. wait for time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for time, t erase (minimum 1 ms or 4 ms). 7. clear the erase bit. 8. wait for time, t nvh (minimum 5 s). 9. clear the hven bit. 10. wait for a time, t rcv , (typically 1 s) after which the memory can be accessed in normal read mode. notes a. programming and erasing of flash locations can not be performed by code being executed from the same flash array. b. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. however, care must be taken to ensure that these operations do not access any address within the flash array memory space such as the cop control register (copctl) at $ffff. c. it is highly recommended that interrupts be disabled during program/erase operations. in applications that require more than 1000 program /erase cycles, use the 4 ms page erase specification to get improved long-term reliability. any application can use this 4 ms page erase specification. however, in applications where a flash location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time. 2.6.6 flash-1 program operation programming of the flash-1 memory is done on a ro w basis. a row consists of 64 consecutive bytes with address ranges as follows: ? $xx00 to $xx3f ? $xx40 to $xx7f ? $xx80 to $xxbf ? $xxc0 to $xxff memory mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 50 freescale semiconductor during the programming cycle, make sure that all addr esses being written to fit within one of the ranges specified above. attempts to program addresses in different row ranges in one programming cycle will fail. use this step-by-step procedure to program a row of flash-1 memory. note only bytes which are currently $ff may be programmed. 1. set the pgm bit in the flash-1 control register (fl1cr). this configures the memory for program operation and enables the latching of address and data programming. 2. read the flash-1 block protect register (fl1bpr). 3. write to any flash-1 address within the row address range desired with any data. 4. wait for time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for time, t pgs (minimum 5 s). 7. write data byte to the flash-1 address to be programmed. 8. wait for time, t prog (minimum 30 s). 9. repeat steps 7 and 8 until all the bytes within the row are programmed. 10. clear the pgm bit. 11. wait for time, t nvh (minimum 5 s) 12. clear the hven bit. 13. wait for a time, t rcv , (typically 1 s) after which the memory can be accessed in normal read mode. the flash programming algorithm flowchart is shown in figure 2-6 . notes a. programming and erasing of flash locations can not be performed by code being executed from the same flash array. b. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. however, care must be taken to ensure that these operations do not access any address within the flash array memory space such as the cop control register (copctl) at $ffff. c. it is highly recommended that interrupts be disabled during program/erase operations. d. do not exceed t prog maximum or t hv maximum. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x 64) t hv maximum e. the time between each flash address change (step 7 to step 7), or the time between the last flash address programmed to clearing the pgm bit (ste p 7 to step 10) must not exceed the maximum programming time, t prog maximum. f. be cautious when programming the flash-1 array to ensure that non-flash locations are not used as the address that is written to when selecting either the desired row address range in step 3 of the algorithm or the byte to be programmed in step 7 of the algorithm. flash-1 memory (flash-1) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 51 figure 2-6. flash-1 programming algorithm flowchart set hven bit read the flash block wait for a time, t nvs set pgm bit wait for a time, t pgs wait for a time, t prog clear pgm bit clear hven bit completed programming this row? yes no end of programming 1 2 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (64 bytes) of flash memory protect register write any data to any flash address within the row address range desired write data to the flash address to be programmed wait for a time, t nvh wait for a time, t rcv notes: the time between each flash address change (step 7 to step 7) or the time between the last flash address programmed to clearing pgm bit (step 7 to step10) must not exceed the maximum programming time, t prog , maximum. this row program algorithm assumes the row/s to be programmed are initially erased. memory mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 52 freescale semiconductor 2.6.7 low-power modes the wait and stop instructions will place the mcu in low power-consumption standby modes. 2.6.7.1 wait mode putting the mcu into wait mode while the flash is in read mode does not affect the operation of the flash memory directly; ho wever, no memory activity will ta ke place since the cpu is inactive. the wait instruction should not be executed while performing a program or erase operation on the flash. wait mode will suspend any flash progra m/erase operations and leave the memory in a standby mode. 2.6.7.2 stop mode putting the mcu into stop mode while the flash is in read mode does not affect the operation of the flash memory directly; ho wever, no memory activity will ta ke place since the cpu is inactive. the stop instruction should not be executed while performing a program or erase operation on the flash. stop mode will suspend any flash program/erase operations and leave the memory in a standby mode. note standby mode is the power saving mode of the flash module, in which all internal control signals to the flash are inactive and the current consumption of the flash is minimum. 2.7 flash-2 memory (flash-2) this subsection describes the operation of the emb edded flash-2 memory. this memory can be read, programmed, and erased from a single external su pply. the program and erase operations are enabled through the use of an internal charge pump. 2.7.1 functional description the flash-2 memory is a non-continuous array consisting of a total of 29,822 bytes. an erased bit reads as a 1 and a programmed bit reads as a 0. memory in the flash-2 array is organized into rows within pages. there are two rows of memory per page with 64 bytes per row. the minimum erase bl ock size is a single page, 128 bytes. programming is performed on a per-row basis, 64 bytes at a time. pr ogram and erase operations are facilitated through control bits in the flash-2 control register (fl2cr) . details for these operations appear later in this subsection. the flash-2 memory map consists of: ? $0462?$04ff: user memory (158 bytes) ? $0980?$1b7f: user memory (4608 bytes) ? $1e20?$7fff: user memory (25056 bytes) ? $ff81: flash-2 block protect register (fl2bpr) note fl2bpr physically re sides within flash-1 memory addressing space ? $fe08: flash-2 control register (fl2cr) flash-2 memory (flash-2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 53 programming tools are available from freescale. cont act your local freescale representative for more information. note a security feature prevents viewing of the flash contents. (1) 2.7.2 flash-2 control an d block protect registers the flash-2 array has two registers that control its operation, the flash-2 control register (fl2cr) and the flash-2 block protect register (fl2bpr). 2.7.2.1 flash-2 control register the flash-2 control register (fl2cr) controls flash-2 program and erase operations. hven ? high-voltage enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operations in the array. hven can only be set if either pgm = 1 or erase = 1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit setting this read/write bit configures the fl ash-2 array for mass or page erase operation. 1 = mass erase operation selected 0 = page erase operation selected erase ? erase control bit this read/write bit configures t he memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be set at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures the memory for progr am operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users. address: $fe08 bit 7654321bit 0 read:0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 2-7. flash-2 control register (fl2cr) memory mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 54 freescale semiconductor 2.7.2.2 flash-2 block protect register the flash-2 block protect register (fl2bpr) is im plemented as a byte within the flash-1 memory; therefore, can only be written during a flash-1 programming sequence. the value in this register determines the starting location of the protected range within the flash-2 memory. note the flash-2 block protect register (fl2bpr) controls the block protection for the flash-2 array. however, fl 2bpr is implemented within the flash-1 memory array and therefore, the flash-1 control register (fl1cr) must be used to program/erase fl2bpr. fl2bpr[7:0] ? block protect register bits 7 to 0 these eight bits represent bits [14:7] of a 16-bit memory address. bit 15 is a 0 and bits [6:0] are 0s. the resultant 16-bit address is used for specifying the start address of the flash-2 memory for block protection. flash-2 is protected from this start address to the end of flash-2 memory at $7fff. with this mechanism, the protect start addres s can be $xx00 and $xx80 (128 byte page boundaries) within the flash-2 array. figure 2-9. flash-2 block protect start address address: $ff81 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset figure 2-8. flash-2 block protect register (fl2bpr) table 2-3. flash-2 protected ranges fl2bpr[7:0] protected range $ff no protection $fe $7f00?$7fff $fd $0b $7e80?$7fff $0580?$7fff $0a $0500?$7fff $09 $0480?$7fff $08 $04 $0462?$7fff $0462?$7fff $03 $0462?$7fff $02 $0462?$7fff $01 $0462?$7fff $00 $0462?$7fff 0 flbpr value 16-bit memory address 0000000 start address of flash block protect flash-2 memory (flash-2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 55 decreasing the value in fl2bpr by one increa ses the protected range by one page (128 bytes). however, programming the block protect register with $fe protects a range twice that size, 256 bytes, in the corresponding array. $fe means that locations $7f00?$7fff are protected in flash-2. the flash memory does not exist at some location s. the block protection range configuration is unaffected if flash memory does not exist in that range. refer to figure 2-1 and make sure that the desired locations are protected. 2.7.3 flash-2 block protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made fo r protecting blocks of memory from unintentional erase or program operations due to system malfunction. this protec tion is done by using the flash-2 block protection register (fl2bpr). fl2bpr determines the range of the flash-2 memory which is to be protected. the range of the protected area starts from a locati on defined by fl2bpr and ends at the bottom of the flash-2 memory ($7fff). when the memory is protec ted, the hven bit can not be set in either erase or program operations. note in performing a program or erase operation, the flash-2 block protect register must be read after setting the pgm or erase bit and before asserting the hven bit. when the flash-2 block protect register is programmed with all 0?s, the entire memory is protected from being programmed and erased. when all the bits are erased (all 1?s), the entire memory is accessible for program and erase. when bits within fl2bpr are programmed (0), they lock a block of memory address ranges as shown in 2.7.2.2 flash-2 block protect register . if fl2bpr is programmed with any value other than $ff, the protected block of flash memory can not be erased or programmed. note the vector locations and the flash block protect registers are located in the same page. fl1bpr and fl2bpr are not protected with special hardware or software. therefore, if this page is not protected by fl1bpr and the vector locations are erased by either a page or a mass erase operation, both fl1bpr and fl2bpr will also get erased. 2.7.4 flash-2 mass erase operation use this step-by-step procedure to erase the entire flash-2 memory: 1. set both the erase bit and the mass bit in the flash-2 control register (fl2cr). 2. read the flash-2 block protect register (fl2bpr). note mass erase is disabled whenever any bl ock is protected (fl2bpr does not equal $ff). 3. write to any flash-2 address within the flash-2 array with any data. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t merase (minimum 4 ms). 7. clear the erase and mass bits. memory mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 56 freescale semiconductor 8. wait for a time, t nvhl (minimum 100 s). 9. clear the hven bit. 10. wait for a time, t rcv , (typically 1 s) after which the memory can be accessed in normal read mode. notes a. programming and erasing of flash locations can not be performed by code being executed from the same flash array. b. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. however, care must be taken to ensure that these operations do not access any address within the flash array memory space such as the cop control register (copctl) at $ffff. c. it is highly recommended that interrupts be disabled during program/erase operations. 2.7.5 flash-2 pa ge erase operation use this step-by-step procedure to erase a page (128 bytes) of flash-2 memory: 1. set the erase bit and clear the mass bit in the flash-2 control register (fl2cr). 2. read the flash-2 block protect register (fl2bpr). 3. write any data to any flash-2 address within the address range of the page (128 byte block) to be erased. 4. wait for time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for time, t erase (minimum 1 ms or 4 ms). 7. clear the erase bit. 8. wait for time, t nvh (minimum 5 s). 9. clear the hven bit. 10. wait for a time, t rcv , (typically 1 s) after which the memory can be accessed in normal read mode. notes a. programming and erasing of flash locations can not be performed by code being executed from the same flash array. b. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. however, care must be taken to ensure that these operations do not access any address within the flash array memory space such as the cop control register (copctl) at $ffff. c. it is highly recommended that interrupts be disabled during program/erase operations. in applications that require more than 1000 program /erase cycles, use the 4 ms page erase specification to get improved long-term reliability. any application can use this 4 ms page erase specification. however, in applications where a flash location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time. flash-2 memory (flash-2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 57 2.7.6 flash-2 program operation programming of the flash memory is done on a row basi s. a row consists of 64 consecutive bytes with address ranges as follows: ? $xx00 to $xx3f ? $xx40 to $xx7f ? $xx80 to $xxbf ? $xxc0 to $xxff during the programming cycle, make sure that all addr esses being written to fit within one of the ranges specified above. attempts to program addresses in different row ranges in one programming cycle will fail. note only bytes which are currently $ff may be programmed. use this step-by-step procedure to program a row of flash-2 memory: 1. set the pgm bit in the flash-2 control register (fl2cr). this configures the memory for program operation and enables the latching of address and data programming. 2. read the flash-2 block protect register (fl2bpr). 3. write to any flash-2 address within the row address range desired with any data. 4. wait for time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for time, t pgs (minimum 5 s). 7. write data byte to the flash-2 address to be programmed. 8. wait for time, t prog (minimum 30 s). 9. repeat step 7 and 8 until all the bytes within the row are programmed. 10. clear the pgm bit. 11. wait for time, t nvh (minimum 5 s). 12. clear the hven bit. 13. wait for a time, t rcv , (typically 1 s) after which the memory can be accessed in normal read mode. the flash programming algorithm flowchart is shown in figure 2-10 . notes a. programming and erasing of flash locations can not be performed by code being executed from the same flash array. b. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. however, care must be taken to ensure that these operations do not access any address within the flash array memory space such as the cop control register (copctl) at $ffff. c. it is highly recommended that interrupts be disabled during program/erase operations. d. do not exceed t prog maximum or t hv maximum. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x 64) t hv maximum memory mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 58 freescale semiconductor e. the time between each flash address change (step 7 to step 7), or the time between the last flash address programmed to clearing the pgm bit (ste p 7 to step 10) must not exceed the maximum programming time, t prog maximum. f. be cautious when programming the flash-2 array to ensure that non-flash locations are not used as the address that is written to when selecting either the desired row address range in step 3 of the algorithm or the byte to be programmed in step 7 of the algorithm. 2.7.7 low-power modes the wait and stop instructions will place the mcu in low power-consumption standby modes. 2.7.7.1 wait mode putting the mcu into wait mode while the flash is in read mode does not affect the operation of the flash memory directly; ho wever, no memory activity will ta ke place since the cpu is inactive. the wait instruction should not be executed while performing a program or erase operation on the flash. wait mode will suspend any flash progra m/erase operations and leave the memory in a standby mode. 2.7.7.2 stop mode putting the mcu into stop mode while the flash is in read mode does not affect the operation of the flash memory directly; ho wever, no memory activity will ta ke place since the cpu is inactive. the stop instruction should not be executed while performing a program or erase operation on the flash. stop mode will suspend any flash program/erase operations and leave the memory in a standby mode. note standby mode is the power saving mode of the flash module, in which all internal control signals to the flash are inactive and the current consumption of the flash is minimum. flash-2 memory (flash-2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 59 figure 2-10. flash-2 progr amming algorithm flowchart set hven bit read the flash block wait for a time, t nvs set pgm bit wait for a time, t pgs wait for a time, t prog clear pgm bit clear hven bit completed programming this row? yes no end of programming 1 2 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (64 bytes) of flash memory protect register write any data to any flash address within the row address range desired write data to the flash address to be programmed wait for a time, t nvh wait for a time, t rcv notes: the time between each flash address change (step 7 to step 7) or the time between the last flash address programmed to clearing pgm bit (step 7 to step10) must not exceed the maximum programming time, t prog , maximum. this row program algorith m assumes the row/s to be programmed are initially erased. memory mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 60 freescale semiconductor mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 61 chapter 3 analog-to-digital converter (adc) 3.1 introduction this section describes the 10-bit analog-to-digital converter (adc). 3.2 features features of the adc module include: ? 24 channels with multiplexed input ? linear successive approxi mation with monotonicity ? 10-bit resolution ? single or continuous conversion ? conversion complete flag or conversion complete interrupt ? selectable adc clock ? left or right justified result ? left justified sign data mode 3.3 functional description the adc provides 24 pins for sampling exter nal sources at pins ptg7/ad23?ptg0/ad16, pta7/kbd7/ad15?pta0/kbd0/ad8, and ptb7/ad7?ptb0/ad0. an analog multiplexer allows the single adc converter to select one of 24 adc channels as adc voltage in (v adin ). v adin is converted by the successive approximation register-based analog -to-digital converter. when the conversion is completed, adc places the result in the adc data register and sets a flag or generates an interrupt. see figure 3-2 . 3.3.1 adc port i/o pins ptg7/ad23?ptg0/ad16, pta7/kbd7/ad15?pta0/kbd0/ad8, and ptb7/ad7?ptb0/ad0 are general-purpose i/o (input/output) pins that share wi th the adc channels. the channel select bits define which adc channel/port pin will be used as the inpu t signal. the adc overrides the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and can be used as general-purpose i/o. writes to the port register or data direction register (ddr) will not have any affect on the port pin that is selected by the adc. a read of a port pin in use by the adc will return a 0. analog-to-digital converter (adc) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 62 freescale semiconductor figure 3-1. block diagram highlighting adc block and pins single breakpoint break module system integration module programmable timebase module monitor mode entry serial peripheral 6-channel timer interface module dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash ? 62,078 bytes user ram ? 2048 bytes monitor rom user flash vector space ? 52 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 rst (1) irq (1) interface module interrupt module computer operating properly module pta7/kbd7/ad15? 10-bit analog-to-digital converter module ptc6 (2) ptc5 (2) ptc4 (2, 3) ptc3 (2, 3) ptc2 (2, 3) ptc1/can rx (2, 3) ptc0/can tx (2, 3) ptd7/t2ch1 (2) ptd6/t2ch0 (2) ptd5/t1ch1 (2) ptd4/t1ch0 (2) ptd3/spsck (2) ptd2/mosi (2) ptd1/miso (2) ptd0/ss /mclk (2) pte1/rxd pte0/txd 2-channel timer interface module enhanced serial interface module security module power-on reset module memory map module configuration register 1?2 module power v ss v dd v ssa v dda 1. pin contains in tegrated pullup device. 2. ports are software configurable with pullup device if input port or pullup/pulldown device for keyboard input. 3. higher current drive port pins v ddad /v refh v ssad /v refl pte5?pte2 communications clock generator module cgmxfc phase locked loop 1?8 mhz oscillator portb ddrb ptb7/ad7? portf ddrf ptf7/t2ch5 module portg ddrg ptg7/ad23? ptf6/t2ch4 ptf5/t2ch3 ptf4/t2ch2 ptf3?pft0 (3) mscan module pta0/kbd0/ad8 (2) ptb0/ad0 ptg0/ad16 functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 63 figure 3-2. adc block diagram 3.3.2 voltage conversion when the input voltage to the adc equals v refh , the adc converts the signal to $3ff (full scale). if the input voltage equals v refl , the adc converts it to $000. input voltages between v refh and v refl are a straight-line linear conversion. note the adc input voltage must always be greater than v ssad and less than v ddad . connect the v ddad pin to the same voltage potential as the v dd pin, and connect the v ssad pin to the same voltage potential as the v ss pin. the v ddad pin should be routed carefully for maximum noise immunity. internal data bus read ddrx write ddrx reset write ptx read ptx ptx ddrx ptx interrupt logic channel select adc clock generator conversion complete adc (v adin ) adc clock cgmxclk bus clock adch4?adch0 adc data register aien coco disable disable adc channel x adiv2?adiv0 adiclk voltage in analog-to-digital converter (adc) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 64 freescale semiconductor 3.3.3 conversion time conversion starts after a write to the adc status and control register (adscr). one conversion will take between 16 and 17 adc clock cycles. the adivx and ad iclk bits should be set to provide a 1-mhz adc clock frequency. 3.3.4 conversion in continuous conversion mode, the adc data register will be filled with new data after each conversion. data from the previous conversion will be over written whether that data has been read or not. conversions will continue until the adco bit is cleared. the coco bit is set after each conversion and will stay set until the next read of the adc data register. in single conversion mode, conversion begins with a write to t he adscr. only one conversion occurs between writes to the adscr. when a conversion is in process and the adscr is written, the current conversion data should be discarded to prevent an incorrect reading. 3.3.5 accuracy and precision the conversion process is monot onic and has no missing codes. 3.3.6 result justification the conversion result may be formatted in four different ways: 1. left justified 2. right justified 3. left justified sign data mode 4. 8-bit truncation mode all four of these modes are controlled using mode0 and mode1 bits located in the adc clock register (adclk). left justification will place the eight most signific ant bits (msb) in the corresponding adc data register high, adrh. this may be useful if the result is to be treated as an 8-bit result where the two least significant bits (lsb), located in the adc data regist er low, adrl, can be ignored. however, adrl must be read after adrh or else the interlocking wi ll prevent all new conversions from being stored. right justification will place only the two msbs in the corresponding adc data register high, adrh, and the eight lsbs in adc data register low, adrl. this mode of operation typically is used when a 10-bit unsigned result is desired. 16 to 17 adc cycles adc frequency conversion time = number of bus cycles = conversion time bus frequency monotonicity mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 65 left justified sign data mode is similar to left just ified mode with one exception. the msb of the 10-bit result, ad9 located in adrh, is complemented. th is mode of operation is useful when a result, represented as a signed magnitude from mid-scale, is needed. finally, 8-bit truncation mode will place the eight msbs in the adc data register low, a drl. the two lsbs are dropped. this mode of operation is used when compatibility with 8-bit adc designs are required. no interlocking between adrh and adrl is present. note quantization error is affected when only the most significant eight bits are used as a result. see figure 3-3 . figure 3-3. bit truncation mode error 3.4 monotonicity the conversion process is monot onic and has no missing codes. 3.5 interrupts when the aien bit is set, the adc module is c apable of generating cpu interrupts after each adc conversion. a cpu interrupt is generated if the coco bit is a 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. ideal 10-bit characteristic with quantization = 1/2 ideal 8-bit characteristic with quantization = 1/2 10-bit truncated to 8-bit result when truncation is used, error from ideal 8-bit = 3/8 lsb due to non-ideal quantization. 000 001 002 003 004 005 006 007 008 009 00a 00b 000 001 002 003 8-bit result 10-bit result input voltage represented as 10-bit input voltage represented as 8-bit 1/2 2 1/2 4 1/2 6 1/2 8 1/2 1 1/2 3 1/2 5 1/2 7 1/2 9 1/2 1/2 2 1/2 1 1/2 analog-to-digital converter (adc) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 66 freescale semiconductor 3.6 low-power modes the wait and stop instruction can put the mcu in low power- consumption standby modes. 3.6.1 wait mode the adc continues normal operation du ring wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting ad ch4?adch0 bits in the adc status and control register before executing the wait instruction. 3.6.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode after an external interrupt. allow one conversion cycle to stabi lize the analog circuitry. 3.7 i/o signals the adc module has eight pins shared with port a and the kbi module: pta7/kbd7/ad15?pta0/kbd0/ad8 the adc module has eight pi ns shared with port b: ptb7/ad7?ptb0/ad0 the adc module has eight pi ns shared with port g: ptg7/ad23?ptg0/ad16 3.7.1 adc analog power pin (v ddad ) the adc analog portion uses v ddad as its power pin. connect the v ddad pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v ddad for good results. note for maximum noise immunity, route v ddad carefully and place bypass capacitors as close as possible to the package. v ddad and v refh are bonded internally. 3.7.2 adc analog ground pin (v ssad ) the adc analog portion uses v ssad as its ground pin. connect the v ssad pin to the same voltage potential as v ss . note route v ssad cleanly to avoid any offset errors. v ssad and v refl are bonded internally. i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 67 3.7.3 adc voltage reference high pin (v refh ) the adc analog portion uses v refh as its upper voltage reference pin. by default, connect the v refh pin to the same voltage potential as v dd . external filtering is often necessary to ensure a clean v refh for good results. any noise present on this pin will be reflected and possibly m agnified in a/d conversion values. note for maximum noise immunity, route v refh carefully and place bypass capacitors as close as possibl e to the package. routing v refh close and parallel to v refl may improve common mode noise rejection. v ddad and v refh are bonded internally. 3.7.4 adc voltage reference low pin (v refl ) the adc analog portion uses v refl as its lower voltage reference pin. by default, connect the v refl pin to the same voltage potential as v ss . external filtering is often necessary to ensure a clean v refl for good results. any noise present on this pin will be reflec ted and possibly magnified in a/d conversion values. note for maximum noise immunity, route v refl carefully and, if not connected to v ss , place bypass capacitors as cl ose as possible to the package. routing v refh close and parallel to v refl may improve common mode noise rejection. v ssad and v refl are bonded internally. 3.7.5 adc voltage in (v adin ) v adin is the input voltage signal from one of the 24 adc channels to the adc module. 3.8 i/o registers these i/o registers control and monitor adc operation: ? adc status and control register (adscr) ? adc data register (adrh and adrl) ? adc clock register (adclk) analog-to-digital converter (adc) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 68 freescale semiconductor 3.8.1 adc status and control register function of the adc status and control register (adscr) is described here. coco ? conversions complete bit in non-interrupt mode (aien = 0), coco is a read-only bit that is set at the end of each conversion. coco will stay set until cleared by a read of the adc data register. reset clears this bit. in interrupt mode (aien = 1), coco is a read-only bit that is not set at the end of a conversion. it always reads as a 0. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0) or cpu interrupt enabled (aien = 1) note the write function of the coco bit is reserved. when writing to the adscr register, always have a 0 in the coco bit position. aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at th e end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conversion is completed between writes to the adscr when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch4?adch0 ? adc channel select bits adch4?adch0 form a 5-bit field which is used to select one of 32 adc channels. only 24 channels, ad23?ad0, are available on this m cu. the channels are detailed in table 3-1 . care should be taken when using a port pin as both an analog and digita l input simultaneously to prevent switching noise from corrupting the analog signal. see table 3-1 . the adc subsystem is turned off when the channel select bits are all set to 1. this feature allows for reduced power consumption for the mcu when the adc is not being used. note recovery from the disabled state requi res one conversion cycle to stabilize. address: $003c bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: r reset:00011111 r= reserved figure 3-4. adc status and control register (adscr) i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 69 the voltage levels supplied from inte rnal reference nodes, as specified in table 3-1 , are used to verify the operation of the adc converter both in production test and for user applications. table 3-1. mux channel select (1) 1. if any unused channels are selected, the resulting adc conv ersion will be unknown or re- served. adch4 adch3 adch2 adch1 adch0 input select 00000 ptb0/ad0 00001 ptb1/ad1 00010 ptb2/ad2 00011 ptb3/ad3 00100 ptb4/ad4 00101 ptb5/ad5 00110 ptb6/ad6 00111 ptb7/ad7 0 1 0 0 0 pta0/kbd0/ad8 0 1 0 0 1 pta1/kbd1/ad9 0 1 0 1 0 pta2/kbd2/ad10 0 1 0 1 1 pta3/kbd3/ad11 0 1 1 0 0 pta4/kbd4/ad12 0 1 1 0 1 pta5/kbd5/ad13 0 1 1 1 0 pta6/kbd6/ad14 0 1 1 1 1 pta7/kbd7/ad15 1 0 0 0 0 ptg0/ad16 1 0 0 0 1 ptg1/ad17 1 0 0 1 0 ptg2/ad18 1 0 0 1 1 ptg3/ad19 1 0 1 0 0 ptg4/ad20 1 0 1 0 1 ptg5/ad21 1 0 1 1 0 ptg6/ad22 1 0 1 1 1 ptg7/ad23 1 1 1 1 0 1 0 0 0 0 unused 11101 v refh 11110 v refl 1 1 1 1 1 adc power off analog-to-digital converter (adc) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 70 freescale semiconductor 3.8.2 adc data register high and data register low 3.8.2.1 left justified mode in left justified mode, the adrh register holds the eight msbs of the 10-bit result. the adrl register holds the two lsbs of the 10-bit result. all other bits read as 0. adrh and adrl are updated each time an adc single ch annel conversion completes. reading adrh latches the contents of adrl until adrl is read. all subs equent results will be lost until the adrh and adrl reads are completed. 3.8.2.2 right justified mode in right justified mode, the adrh register holds the two msbs of the 10-bit result. all other bits read as 0. the adrl regi ster holds the eight lsbs of the 10-bit result. adrh and adrl are updated each time an adc single ch annel conversion completes. reading adrh latches the contents of adrl until adrl is read. all subs equent results will be lost until the adrh and adrl reads are completed. address: $003d adrh bit 7654321bit 0 read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write: reset: unaffected by reset address: $003e adrl read:ad1ad0000000 write: reset: unaffected by reset = unimplemented figure 3-5. adc data register high (adrh) and low (adrl) address: $003d adrh bit 7654321bit 0 read:000000ad9ad8 write: reset: unaffected by reset address: $003e adrl read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: unaffected by reset = unimplemented figure 3-6. adc data register high (adrh) and low (adrl) i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 71 3.8.2.3 left justified signed data mode in left justified signed data mode, the adrh register holds the eight msbs of the 10-bit result. the only difference from left justified mode is that the ad9 is complemented. the adrl register holds the two lsbs of the 10-bit result. all other bits read as 0. adrh and adrl are updated each time an adc single channel conversion completes. reading adrh latches the contents of adrl until adrl is read. all subsequent results will be lost until the adrh and adrl reads are completed. 3.8.2.4 eight bit truncation mode in 8-bit truncation mode, the adrl r egister holds the eight msbs of t he 10-bit result. the adrh register is unused and reads as 0. the adrl register is updated each time an adc single channel conversion completes. in 8-bit mode, the adrl regi ster contains no interlocking with adrh. address: $003d bit 7654321bit 0 read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write: reset: unaffected by reset address: $003e read:ad1ad0000000 write: reset: unaffected by reset = unimplemented figure 3-7. adc data register high (adrh) and low (adrl) address: $003d adrh bit 7654321bit 0 read:00000000 write: reset: unaffected by reset address: $003e adrl read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write: reset: unaffected by reset = unimplemented figure 3-8. adc data register high (adrh) and low (adrl) analog-to-digital converter (adc) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 72 freescale semiconductor 3.8.3 adc clock register the adc clock register (adclk) selects the clock frequency for the adc. adiv2?adiv0 ? adc clock prescaler bits adiv2?adiv0 form a 3-bit field which selects the divi de ratio used by the adc to generate the internal adc clock. table 3-2 shows the available clock configurat ions. the adc clock should be set to approximately 1 mhz. adiclk ? adc input clock select bit adiclk selects either the bus clock or the oscill ator output clock (cgmxclk) as the input clock source to generate the internal adc clock. re set selects cgmxclk as the adc clock source. 1 = internal bus clock 0 = oscillator output clock (cgmxclk) the adc requires a clock rate of approximately 1 mhz for correct operation. if the selected clock source is not fast enough, the adc will generate incorrect conversions. see 21.10 5.0-volt adc characteristics . mode1 and mode0 ? modes of result justification bits mode1 and mode0 select among four modes of ope ration. the manner in wh ich the adc conversion results will be placed in the adc data registers is controlled by these modes of operation. reset returns right-justified mode. 00 = 8-bit truncation mode 01 = right justified mode 10 = left justified mode 11 = left justified signed data mode address: $003f bit 7654321bit 0 read: adiv2 adiv1 adiv0 adiclk mode1 mode0 r 0 write: reset:00000100 = unimplemented r = reserved figure 3-9. adc clock register (adclk) table 3-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x (1) 1. x = don?t care x (1) adc input clock 16 f adic = f cgmxclk or bus frequency adiv[2:0] ? 1 mhz mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 73 chapter 4 clock generator module (cgm) 4.1 introduction this section describes the clock generator modul e. the cgm generates the crystal clock signal, cgmxclk, which operates at the frequency of the cr ystal. the cgm also generates the base clock signal, cgmout, which is based on either the crysta l clock divided by two or the phase-locked loop (pll) clock, cgmvclk, divided by two. in user mode, cg mout is the clock from which the sim derives the system clocks, including the bus clock, which is at a frequency of cgmout/2. the p ll is a fully functional frequency generator designed for use with crystals or ceramic resonators. the pll can generate a maximum bus frequency of 8 mhz using a 1-8m hz crystal or external clock source. 4.2 features features of the cgm include: ? phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal reference ? high-frequency crystal operation with low-power operation and high-output frequency resolution ? programmable hardware voltage-controlled oscillator (vco) for low-jitter operation ? automatic bandwidth control mode for low-jitter operation ? automatic frequency lock detector ? cpu interrupt on entry or exit from locked condition ? configuration register bit to allow oscillator operation during stop mode 4.3 functional description the cgm consists of three major submodules: ? crystal oscillator circuit ? the crystal oscillat or circuit generates the constant crystal frequency clock, cgmxclk. ? phase-locked loop (pll) ? the pll generates the programmable vco frequency clock, cgmvclk. ? base clock selector circuit ? this software-cont rolled circuit selects either cgmxclk divided by two or the vco clock, cgmvclk, divided by two as the base cl ock, cgmout. the sim derives the system clocks from ei ther cgmout or cgmxclk. figure 4-1 shows the structure of the cgm. clock generator module (cgm) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 74 freescale semiconductor figure 4-1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator automatic mode control lock detector clock cgmxclk cgmout cgmvdv cgmvclk simoscen (from sim) oscillator (osc) interrupt control cgmint pll analog 2 cgmrclk osc2 osc1 select circuit v dda cgmxfc v ssa lock auto acq vpr1?vpr0 pllie pllf mul11?mul0 vrs7?vrs0 osceninstop (from config) (to: sim, tbm, adc, mscan) phase-locked loop (pll) a b s * * when s = 1, cgmout = b simdiv2 (from sim) (to sim) (to sim) functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 75 4.3.1 crystal os cillator circuit the crystal oscillator circuit consists of an inverting am plifier and an external crystal. the osc1 pin is the input to the amplifier and the osc2 pin is the out put. the simoscen signal from the system integration module (sim) or the osceninstop bit in the config register enable the crystal oscillator circuit. the cgmxclk signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cgmxclk is then buffered to pr oduce cgmrclk, the pll reference clock. cgmxclk can be used by other modules which require precise timing for operation. the duty cycle of cgmxclk is not guaranteed to be 50% and depends on ex ternal factors, including the crystal and related external components. an externally generated clock also can feed the osc1 pin of the crystal oscillator circuit. connect the external clock to th e osc1 pin and let the osc2 pin float. 4.3.2 phase-locked loop circuit (pll) the pll is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. the pll can change between acquisition and tracking modes either automatically or manually. 4.3.3 pll circuits the pll consists of these circuits: ? voltage-controlled oscillator (vco) ? modulo vco frequency divider ? phase detector ? loop filter ? lock detector the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, incl uding supply and cgmxfc noise. the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cgmxfc pin changes the frequency wi thin this range. by design, f vrs is equal to the nominal center-of-range frequency, f nom , (71.4 khz) times a linear factor, l, and a power-of-two factor, e, or (l 2 e )f nom . cgmrclk is the pll reference clock, a buffered ve rsion of cgmxclk. cgmrclk runs at a frequency, f rclk . the vco?s output clock, cgmvclk, running at a frequency, f vclk , is fed back through a programmable modulo divider. the modulo divider reduces the vco cloc k by a factor, n. the dividers output is the vco feedback clock, cgmvdv, running at a frequency, f vdv =f vclk /(n). (for more information, see 4.3.6 programming the pll .) the phase detector then compares the vco feedback cloc k, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase difference between the two signals. the loop filter then slightly alters the dc voltage on the external capacitor co nnected to cgmxfc based on the width and direction of the correction pulse. the fi lter can make fast or slow corrections depending on its mode, described in 4.3.4 acquisition and tracking modes . the value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the frequencies of the vco feedback clock, cgmvdv, and the reference clock, cgmrclk. therefore, the speed of the lock detector is directly proportional to the reference clock generator module (cgm) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 76 freescale semiconductor frequency, f rclk . the circuit determines the mode of the pll and the lock condition based on this comparison. 4.3.4 acquisition and tracking modes the pll filter is manually or automatically configurable into one of two operating modes: ? acquisition mode ? in acquisition mode, the filt er can make large frequency corrections to the vco. this mode is used at pll start up or w hen the pll has suffered a severe noise hit and the vco frequency is far off the desired freq uency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register. (see 4.5.2 pll bandwidth control register .) ? tracking mode ? in tracking mode, the filter makes only small corrections to the frequency of the vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode when the vco frequency is nearly correct, such as when the pll is selected as the base clock source. (see 4.3.8 base clock selector circuit .) the pll is automatically in tracking mode when not in acqui sition mode or when the acq bit is set. 4.3.5 manual and automa tic pll bandwidth modes the pll can change the bandwidth or operational mode of the loop filter manua lly or automatically. automatic mode is recommended for most users. in automatic bandwidth control mode (auto = 1), th e lock detector automatically switches between acquisition and tracking modes. automatic bandwidth c ontrol mode also is used to determine when the vco clock, cgmvclk, is safe to use as th e source for the base clock, cgmout. (see 4.5.2 pll bandwidth control register .) if pll interrupts are enabled, the software can wait for a pll interrupt request and then check the lock bit. if interrupts are disabled, software can poll the lock bit continuously (for example, during pll start up) or at periodic intervals. in either case, when the lock bit is set, the vco clock is safe to use as the source for the base clock. (see 4.3.8 base clock selector circuit .) if the vco is selected as the source for th e base clock and the lock bit is clear, the pll has suffered a severe noise hit and the software must take appropriate action, depending on the application. (see 4.6 interrupts for information and precautions on using interrupts.) the following conditions apply when the p ll is in automatic bandwidth control mode: ?the acq bit (see 4.5.2 pll bandwidth control register .) is a read-only indicator of the mode of the filter. (see 4.3.4 acquisition and tracking modes .) ?the acq bit is set when the vco frequency is within a certain tolerance and is cleared when the vco frequency is out of a certain tolerance. (see 4.8 acquisition/lock time specifications for more information.) ? the lock bit is a read-only indica tor of the locked state of the pll. ? the lock bit is set when the vco frequency is with in a certain tolerance and is cleared when the vco frequency is out of a certain tolerance. (see 4.8 acquisition/lock time specifications for more information.) ? cpu interrupts can occur if enabled (pllie = 1) when the pll?s lock c ondition changes, toggling the lock bit. (see 4.5.1 pll control register .) the pll also may operate in manual mode (auto = 0) . manual mode is used by systems that do not require an indicator of the lock condition for proper operation. such systems typically operate well below f busmax . functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 77 the following conditions apply when in manual mode: ?acq is a writable control bit that controls the mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. ? before entering tracking mode (acq = 1), software must wait a given time, t acq (see 4.8 acquisition/lock time specifications .), after turning on the pll by setting pllon in the pll control register (pctl). ? software must wait a given time, t al , after entering tracking mode before selecting the pll as the clock source to cgmout (bcs = 1). ? the lock bit is disabled. ? cpu interrupts from the cgm are disabled. 4.3.6 programming the pll use the following procedure to program the pll. for reference, the variables used and their meaning are shown in table 4-1 . note the round function in the following equations means that the real number should be rounded to the nearest integer number. 1. choose the desired bus frequency, f busdes . 2. calculate the desired vco frequency (f our times the desired bus frequency). f vclkdes = 4 x f busdes 3. choose a practical pll (crystal) reference frequency, f rclk . typically, the reference crystal is 1?8 mhz. frequency errors to the pll are corrected at a rate of f rclk . for stability and lock time reduction, this rate must be as fast as possible. the vco frequency must be an integer multiple of this rate. the relationship between the vco frequency, f vclk , and the reference frequency, f rclk , is: f vclk = (n) (f rclk ) n, the range multiplier, must be an integer. table 4-1. variable definitions variable definition f busdes desired bus clock frequency f vclkdes desired vco clock frequency f rclk chosen reference crystal frequency f vclk calculated vco clock frequency f bus calculated bus clock frequency f nom nominal vco center frequency f vrs programmed vco center frequency clock generator module (cgm) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 78 freescale semiconductor in cases where desired bus frequency has some tolerance, choose f rclk to a value determined either by other module requirements (such as modules which are clock ed by cgmxclk), cost requirements, or ideally, as high as the specified range allows. see chapter 21 electrical specifications . after choosing n, the actual bus fr equency can be determined using equation in 2 above. 4. select a vco frequency multiplier, n. 5. calculate and verify the adequacy of the vco and bus frequencies f vclk and f bus . 6. select the vco?s power-of-two range multiplier e, according to table 4-2 . 7. select a vco linear range multiplier, l, where f nom = 71.4 khz 8. calculate and verify the adequacy of the vco programmed center-of-range frequency, f vrs . the center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the pll. f vrs = (l x 2 e ) f nom 9. for proper operation, 10. verify the choice of n, e, and l by comparing f vclk to f vrs and f vclkdes . for proper operation, f vclk must be within the application?s tolerance of f vclkdes , and f vrs must be as close as possible to f vclk . note exceeding the recommended maximum bus frequency or vco frequency can crash the mcu. table 4-2. power-of-two range selectors frequency range e 0 < f vclk 8 mhz 0 8 mhz< f vclk 16 mhz 1 16 mhz< f vclk 32 mhz 2 (1) 1. do not program e to a value of 3. n round f vclkdes f rclk -------------------------- ?? ?? ?? = f vclk n () f rclk = f bus f vclk () 4 ? = l = round f vclk 2 e x f nom f vrs f vclk ? f nom 2 e 2 -------------------------- - functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 79 11. program the pll registers accordingly: a. in the vpr bits of the pll control register (pctl), program the binary equivalent of e. b. in the pll multiplier select register low (p msl) and the pll multiplier select register high (pmsh), program the binary equivalent of n. if using a 1?8 mhz reference, the pmsl register must be reprogrammed from the reset value before enabling the pll. c. in the pll vco range select register (pmrs), program the binary coded equivalent of l. table 4-3 provides numeric examples (register values are in hexadecimal notation): 4.3.7 special programming exceptions the programming method described in 4.3.6 programming the pll does not account for two possible exceptions. a value of 0 for n or l is meaningless when used in the equations given. to account for these exceptions: ? a 0 value for n is interpreted exactly the same as a value of 1. ? a 0 value for l disables the pll and prevents it s selection as the source for the base clock. see 4.3.8 base clock selector circuit . 4.3.8 base clock se lector circuit this circuit is used to select either the crystal cl ock, cgmxclk, or the vco clock, cgmvclk, as the source of the base clock, cgmout. the two input cl ocks go through a transition c ontrol circuit that waits up to three cgmxclk cycles and three cgmvclk cycles to change from one clock source to the other. during this time, cgmout is held in stasis. the outpu t of the transition control circuit is then divided by two to correct the duty cycle. therefore, the bus cl ock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll control register (pctl) selects which clock drives cgmout. the vco clock cannot be selected as the base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be turned on or off simultaneously with the selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the factor l is programmed to a 0. this value would set up a condition inconsistent with the operation of the pll, so that the pll would be disabled and the crysta l clock would be forced as the source of the base clock. table 4-3. numeric example f bus f rclk nel 500 khz 1 mhz 002 0 1b 1.25 mhz 1 mhz 005 0 45 2.0 mhz 1 mhz 008 0 70 2.5 mhz 1 mhz 00a 1 45 3.0 mhz 1 mhz 00c 1 53 4.0 mhz 1 mhz 010 1 70 5.0 mhz 1 mhz 014 2 46 7.0 mhz 1 mhz 01c 2 62 8.0 mhz 1 mhz 020 2 70 clock generator module (cgm) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 80 freescale semiconductor 4.3.9 cgm exte rnal connections in its typical configuration, the cgm requires exte rnal components. five of these are for the crystal oscillator and two or four are for the pll. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 4-2 . figure 4-2 shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: ?crystal, x 1 ? fixed capacitor, c 1 ? tuning capacitor, c 2 (can also be a fixed capacitor) ? feedback resistor, r b ? series resistor, r s the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines. refer to the crystal manufacturer?s data for more info rmation regarding values for c1 and c2. figure 4-2 also shows the external components for the pll: ? bypass capacitor, c byp ? filter network routing should be done with great care to minimize signal cross talk and noise. figure 4-2. cgm external connections osc1 c 1 c 2 simoscen cgmxclk r b x1 r s c byp osc2 cgmxfc v dda note: filter network in box can be replaced wi th a single capacitor, but will degrade stability. v dd osceninstop (from config) r f1 v ssa c f1 c f2 i/o signals mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 81 4.4 i/o signals the following paragraphs de scribe the cgm i/o signals. 4.4.1 crystal amplifi er input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 4.4.2 crystal amplifi er output pin (osc2) the osc2 pin is the output of the cr ystal oscillator inverting amplifier. 4.4.3 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to filter out phase corrections. an external filter network is connected to this pin. (see figure 4-2 .) note to prevent noise problems, the filter network should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other signals across the network. 4.4.4 pll analog power pin (v dda ) v dda is a power pin used by the analog portions of the pll. connect the v dda pin to the same voltage potential as the v dd pin. note route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 4.4.5 pll analog ground pin (v ssa ) v ssa is a ground pin used by the analog portions of the pll. connect the v ssa pin to the same voltage potential as the v ss pin. note route v ssa carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 4.4.6 oscillator e nable signal (simoscen) the simoscen signal comes from the system integr ation module (sim) and enables the oscillator and pll. 4.4.7 oscillator enable in stop m ode bit (osceninstop) osceninstop is a bit in the config2 register that enables the oscillator to continue operating during stop mode. if this bit is set, the osci llator continues running during stop mode. if this bit is not set (default), the oscillator is controlled by the simoscen signal which will disable the oscillator during stop mode. clock generator module (cgm) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 82 freescale semiconductor 4.4.8 crystal output frequency signal (cgmxclk) cgmxclk is the crystal oscillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crys tal oscillator circuit. figure 4-2 shows only the logical relation of cgmxclk to osc1 and osc2 and may not represent the actual circui try. the duty cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of cgmxclk can be unstable at start up. 4.4.9 cgm base cl ock output (cgmout) cgmout is the clock output of the cgm. this signal goes to the sim, which generates the mcu clocks. cgmout is a 50 percent duty cycle clock running at twice the bus frequency. cgmout is software programmable to be either the oscillator output, cg mxclk, divided by two or the vco clock, cgmvclk, divided by two. 4.4.10 cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector. 4.5 cgm registers these registers control and monitor operation of the cgm: ? pll control register (pctl) (see 4.5.1 pll control register .) ? pll bandwidth control register (pbwc) (see 4.5.2 pll bandwidth control register .) ? pll multiplier select register high (pmsh) (see 4.5.3 pll multiplier select register high .) ? pll multiplier select register low (pmsl) (see 4.5.4 pll multiplier select register low .) ? pll vco range select register (pmrs) (see 4.5.5 pll vco range select register .) figure 4-3 is a summary of the cgm registers. addr.register name bit 7654321bit 0 $0036 pll control register (pctl) see page 83. read: pllie pllf pllon bcs r r vpr1 vpr0 write: reset:00100000 $0037 pll bandwidth control register (pbwc) see page 85. read: auto lock acq 0000 r write: reset:00000000 $0038 pll multiplier select high register (pmsh) see page 86. read:0000 mul11 mul10 mul9 mul8 write: reset:00000000 = unimplemented r = reserved figure 4-3. cgm i/o register summary cgm registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 83 4.5.1 pll control register the pll control register (pctl) contains the inte rrupt enable and flag bits, the on/off switch, the base clock selector bit, and the vco power-of-two range selector bits. pllie ? pll interrupt enable bit this read/write bit enables the pll to generate an interrupt request when the lock bit toggles, setting the pll flag, pllf. when the auto bit in the pll b andwidth control register (pbwc) is clear, pllie cannot be written and reads as 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ? pll interrupt flag bit this read-only bit is set whenever the lock bit toggles. pllf generates an interrupt request if the pllie bit also is set. pllf always reads as 0 when the auto bit in the pll bandwidth control register (pbwc) is clear. clear the pllf bit by reading the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition $0039 pll multiplier select low register (pmsl) see page 86. read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 $003a pll vco select range register (pmrs) see page 87. read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 $003b reserved register read:0000 rrrr write: reset:00000001 = unimplemented r = reserved notes: 1. when auto = 0, pllie is forced clear and is read-only. 2. when auto = 0, pllf and lock read as clear. 3. when auto = 1, acq is read-only. 4. when pllon = 0 or vrs7:vrs0 = $0, bcs is forced clear and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. address: $0036 bit 76543 2 1bit 0 read: pllie pllf pllon bcs r r vpr1 vpr0 write: reset:00100 0 00 = unimplemented r = reserved figure 4-4. pll control register (pctl) addr.register name bit 7654321bit 0 figure 4-3. cgm i/o register summary (continued) clock generator module (cgm) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 84 freescale semiconductor note do not inadvertently clear the pllf bit. any read or read-modify-write operation on the pll control register clears the pllf bit. pllon ? pll on bit this read/write bit activates the pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving t he base clock, cgmout (bcs = 1). (see 4.3.8 base clock selector circuit .) reset sets this bit so that the l oop can stabilize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit selects either the crystal oscillator output, cgmxclk, or the vco clock, cgmvclk, as the source of the cgm output , cgmout. cgmout frequency is one-half the frequency of the selected clock. bcs cannot be set while the pllon bit is clear. after toggling bcs, it may take up to three cgmxclk and three cgmv clk cycles to complete the transition from one source clock to the other. during the transit ion, cgmout is held in stasis. (see 4.3.8 base clock selector circuit .) reset clears the bcs bit. 1 = cgmvclk divided by two drives cgmout 0 = cgmxclk divided by two drives cgmout note pllon and bcs have built-in protecti on that prevents the base clock selector circuit from selecting the vco clock as the source of the base clock if the pll is off. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is cl ear. if the pll is off (pllon = 0), selecting cgmvclk requires two writes to the pll control register. (see 4.3.8 base clock selector circuit .). vpr1 and vpr0 ? vco power-of-two range select bits these read/write bits control the vco?s hardware power-of-two range multiplier e that, in conjunction with l controls the hardware center-of-range frequency, f vrs . vpr1:vpr0 cannot be written when the pllon bit is set. reset clears these bits. (see 4.3.3 pll circuits , 4.3.6 programming the pll , and 4.5.5 pll vco range select register .) note verify that the value of the vpr1 and vpr0 bits in the pctl register are appropriate for the given reference and vco clock frequencies before enabling the pll. see 4.3.6 programming the pll for detailed instructions on selecting the proper value for these control bits. table 4-4. vpr1 and vpr0 programming vpr1 and vpr0 e vco power-of-two range multiplier 00 0 1 01 1 2 10 2 (1) 1. do not program e to a value of 3. 4 cgm registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 85 4.5.2 pll bandwidth control register the pll bandwidth control register (pbwc): ? selects automatic or manual (softw are-controlled) bandwidth control mode ? indicates when the pll is locked ? in automatic bandwidth control mode, indicates wh en the pll is in acquisition or tracking mode ? in manual operation, forces the pll into acquisition or tracking mode auto ? automatic bandwidth control bit this read/write bit selects automatic or manual b andwidth control. when initializing the pll for manual operation (auto = 0), clear the acq bit before turning on the pll. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is locked (running at the programmed frequency). wh en the auto bit is clear, lock reads as 0 and has no meaning. the write one function of this bit is reserved for test, so this bit must always be written a 0. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency incorrect or unlocked acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tracking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisition or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. reset clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode address: $0037 bit 7654321bit 0 read: auto lock acq 0000 r write: reset:00000000 = unimplemented r= reserved figure 4-5. pll bandwidth control register (pbwc) clock generator module (cgm) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 86 freescale semiconductor 4.5.3 pll multiplier select register high the pll multiplier select register high (pmsh) cont ains the programming informat ion for the high byte of the modulo feedback divider. mul11?mul8 ? multiplier select bits these read/write bits control the high byte of the modulo feedback divider that selects the vco frequency multiplier n. (see 4.3.3 pll circuits and 4.3.6 programming the pll .) a value of $0000 in the multiplier select registers configures the m odulo feedback divider the same as a value of $0001. reset initializes the registers to $0040 for a default multiply value of 64. note the multiplier select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1). pmsh[7:4] ? unimplemented bits these bits have no function and always read as 0s. 4.5.4 pll multiplier select register low the pll multiplier select register low (pmsl) contains the programming information for the low byte of the modulo feedback divider. note for applications using 1?8 mhz reference frequencies this register must be reprogrammed before enabling the pll. the reset value of this register will cause applications using 1?8 mhz reference frequencies to become unstable if the pll is enabled without programming an appropriate value. the programmed value must not allow the vco clock to exceed 32 mhz. see 4.3.6 programming the pll for detailed instructions on choosing the proper value for pmsl. address: $0038 bit 7654321bit 0 read:0000 mul11 mul10 mul9 mul8 write: reset:00000000 = unimplemented figure 4-6. pll multiplier select register high (pmsh) address: $0038 bit 7654321bit 0 read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 figure 4-7. pll multiplier select register low (pmsl) cgm registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 87 mul7?mul0 ? multiplier select bits these read/write bits control the low byte of the modulo feedback divider that selects the vco frequency multiplier, n. (see 4.3.3 pll circuits and 4.3.6 programming the pll .) mul7?mul0 cannot be written when the pllon bit in the pctl is set. a value of $0000 in the multiplier select registers configures the modulo feedback divider the same as a value of $0001. reset initializes the register to $40 for a default multiply value of 64. note the multiplier select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1). 4.5.5 pll vco range select register the pll vco range select register (pmrs) contai ns the programming information required for the hardware configuration of the vco. note verify that the value of the pmrs register is appropriate for the given reference and vco clock frequencies before enabling the pll. see 4.3.6 programming the pll for detailed instructions on selecting the proper value for these control bits. vrs7?vrs0 ? vco range select bits these read/write bits control the hardware center-of -range linear multiplier l which, in conjunction with e (see 4.3.3 pll circuits , 4.3.6 programming the pll , and 4.5.1 pll control register .), controls the hardware center-of-range frequency, f vrs . vrs7?vrs0 cannot be written when the pllon bit in the pctl is set. (see 4.3.7 special programming exceptions .) a value of $00 in the vco range select register disables the pll and clears the bcs bi t in the pll control register (pctl). (see 4.3.8 base clock selector circuit and 4.3.7 special programming exceptions .). reset initializes the register to $40 for a default range multiply value of 64. note the vco range select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1) and such that the vco clock cannot be selected as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the pll vco range select register must be programmed correctly. incorrect programming can result in failure of the pll to achieve lock. address: $003a bit 7654321bit 0 read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 figure 4-8. pll vco range select register (pmrs) clock generator module (cgm) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 88 freescale semiconductor 4.6 interrupts when the auto bit is set in the pll bandwidth c ontrol register (pbwc), the pll can generate a cpu interrupt request every time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts are enabled or not. when the auto bit is clear, cpu interrupts from the pll are disabled and pllf reads as 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit from lock. when the pll enters lock, the vco clock, cgmvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt, and appropriate precautions s hould be taken. if the application is not frequency sensitive, interrupts should be disabled to prevent pll interrupt service routines from impeding software performance or from exceeding stack limitations. note software can select the cgmvclk divi ded by two as the cgmout source even if the pll is not locked (lock = 0). therefore, software should make sure the pll is locked before setting the bcs bit. 4.7 special modes the wait instruction puts the mcu in low power-consumption standby modes. 4.7.1 wait mode the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl) to save power. less power-sensitive applications can disengage the pll without turning it off, so that the pll clock is immediately available at wait exi t. this would be the case also when the pll is to wake the mcu from wait mode, such as when the pll is first enabled and waiting for lock or lock is lost. 4.7.2 stop mode if the osceninstop bit in the config2 register is cl eared (default), then the stop instruction disables the cgm (oscillator and phase locked loop) and holds low all cgm outputs (cgmxclk, cgmout, and cgmint). if the osceninstop bit in the config2 register is set, then the phase locked loop is shut off but the oscillator will continue to operate in stop mode. 4.7.3 cgm during break interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see 15.7.3 break flag control register .) to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the pllf bit during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write the pll control register during the break state without affecting the pllf bit. acquisition/lock ti me specifications mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 89 4.8 acquisition/lock time specifications the acquisition and lock times of the pll are, in many applications, the most critical pll design parameters. proper design and use of the pll ensure s the highest stability and lowest acquisition/lock times. 4.8.1 acquisition/lock time definitions typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually sp ecified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. therefore, the reaction time is constant in this definition, regardless of the size of the step input. for example, consider a system with a 5 percent acquisiti on time tolerance. if a command instructs the system to change from 0 hz to 1 mhz, the acquisition time is the time taken for the frequency to reach 1 mhz 50 khz. fifty khz = 5% of the 1-mhz step input. if the system is operating at 1 mhz and suffers a ?100-khz noise hit, the acquisition time is the time taken to return from 900 khz to 1 mhz 5 khz. five khz = 5% of the 100-khz step input. other systems refer to acquisition and lock times as t he time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. therefore, the acquisition or lock time varies according to the original error in the output. minor errors may not even be registered. typical pll applications prefer to use this definition beca use the system requires the output frequency to be within a certain tolerance of the desired frequenc y regardless of the size of the initial error. 4.8.2 parametric in fluences on reaction time acquisition and lock times are designed to be as short as possible while still pr oviding the highest possible stability. these reaction times are not constant, however . many factors directly and indirectly affect the acquisition time. the most critical parameter which affects the reaction times of the pll is the reference frequency, f rclk . this frequency is the input to the phase detector and controls how often the pll makes corrections. for stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is under user control via the choice of crystal frequency f xclk . (see 4.3.3 pll circuits and 4.3.6 programming the pll .) another critical parameter is the external filter ne twork. the pll modifies the voltage on the vco by adding or subtracting charge from capacitors in this network. therefore, the rate at which the voltage changes for a given frequency error (thus change in char ge) is proportional to the capacitance. the size of the capacitor also is related to the stability of the pll. if the capacitor is too small, the pll cannot make small enough adjustments to the voltage and the system c annot lock. if the capacitor is too large, the pll may not be able to adjust the voltage in a reasonable time. (see 4.8.3 choosing a filter .) also important is the operating voltage potential applied to v dda . the power supply potential alters the characteristics of the pll. a fixed value is best. va riable supplies, such as batteries, are acceptable if they vary within a known range at very slow sp eeds. noise on the power s upply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the pll. temperature and processing also can affect acquisition time because the electrical characteristics of the pll change. the part operates as spec ified as long as thes e influences stay within the specified limits. clock generator module (cgm) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 90 freescale semiconductor external factors, however, can caus e drastic changes in the operation of the pll. these factors include noise injected into the pll through the filter capacito r, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 4.8.3 choosing a filter as described in 4.8.2 parametric influences on reaction time , the external filter network is critical to the stability and reaction time of the pll. the pl l is also dependent on reference frequency and supply voltage. figure 4-9 shows two types of filter circuits. in low-cost applications, where stability and reaction time of the pll are not critical, the three component filter network shown in figure 4-9 (b) can be replaced by a single capacitor, c f , as shown in shown in figure 4-9 (a). refer to table 4-5 for recommended filter components at various reference frequencies. for reference frequencies between the values listed in the table, extrapolate to the nearest common capacitor valu e. in general, a slightly larger capacitor provides more stability at the expense of increased lock time. figure 4-9. pll filter table 4-5. example filter component values f rclk c f1 c f2 r f1 c f 1 mhz 8.2 nf 820 pf 2k 18 nf 2 mhz 4.7 nf 470 pf 2k 6.8 nf 3 mhz 3.3 nf 330 pf 2k 5.6 nf 4 mhz 2.2 nf 220 pf 2k 4.7 nf 5 mhz 1.8 nf 180 pf 2k 3.9 nf 6 mhz 1.5 nf 150 pf 2k 3.3 nf 7 mhz 1.2 nf 120 pf 2k 2.7 nf 8 mhz 1 nf 100 pf 2k 2.2 nf cgmxfc r f1 c f2 c f1 v ssa cgmxfc c f v ssa (a) (b) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 91 chapter 5 configuration register (config) 5.1 introduction this section describes the configuration registers, config1 and config2. the configuration registers enable or disable these options: ? stop mode recovery time (32 cgmx clk cycles or 4096 cgmxclk cycles) ? cop timeout period (262,128 or 8176 cgmxclk cycles) ?stop instruction ? computer operating properly module (cop) ? low-voltage inhibit (lvi) module control and voltage trip point selection ? enable/disable the oscillator (osc) during stop mode ? enable/disable an extra divide by 128 prescaler in timebase module ? enable for scalable controller area network (mscan) ? selectable clockout (mclk) feature with divide by 1, 2, and 4 of the bus or crystal frequency ? timebase clock select 5.2 functional description the configuration registers are used in the initializatio n of various options. the c onfiguration registers can be written once after each reset. all of the configurat ion register bits are cleared during reset. since the various options affect the operation of the microcontroller unit (mcu), it is recommended that these registers be written immediately after reset. the conf iguration registers are located at $001e and $001f and may be read at anytime. note on a flash device, the options except mscanen and lvi5or3 are one-time writable by the user after each reset. these bits are one-time writable by the user only after each por (power-on reset). the config registers are not in the flash memory but are special registers containing one-time writable latches after each reset. upon a reset, the config registers default to predetermined settings as shown in figure 5-1 and figure 5-2 . configuration register (config) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 92 freescale semiconductor mclksel ? mclk source select bit 1 = crystal frequency 0 = bus frequency mclk1 and mclk0 ? mclk output select bits setting the mclk1 and mclk0 bits enables the ptd0/ss pin to be used as a mclk output clock. once configured for mclk, the ptd data direction r egister for ptd0 is used to enable and disable the mclk output. see table 5-1 for mclk options. mscanen? mscan08 enable bit setting the mscanen enables the mscan08 module and allows the mscan08 to use the ptc0/ptc1 pins. see chapter 12 mscan08 controller (mscan08) for a more detailed description of the mscan08 operation. 1 = enables mscan08 module 0 = disables the mscan08 module note the mscanen bit is cleared by a powe r-on reset (por) only. other resets will leave this bit unaffected. tmbclksel? timebase clock select bit tmbclksel enables an extra divide-by-128 prescaler in the timebase module. setting this bit enables the extra prescaler and clearing this bit disables it. see chapter 17 timebase module (tbm) for a more detailed description of the external clock operation. 1 = enables extra divide-by-128 prescaler in timebase module 0 = disables extra divide-by-128 prescaler in timebase module address: $001e bit 76543 2 1 bit 0 read: 0 mclksel mclk1 mclk0 mscanen tmbclksel osceninstop scibdsrc write: reset:0000see note0 0 1 note: mscanen is only reset via por (power-on reset). = unimplemented figure 5-1. configuration register 2 (config2) table 5-1. mclk output select mclk1 mclk0 mclk frequency 0 0 mclk not enabled 0 1 clock 1 0 clock divided by 2 1 1 clock divided by 4 functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 93 osceninstop ? oscillator enable in stop mode bit osceninstop, when set, will enable the oscillator to continue to generate clocks in stop mode. see chapter 4 clock generator module (cgm) . this function is used to keep the timebase running while the rest of the mcu stops. see chapter 17 timebase module (tbm) . when clear, the oscillator will cease to generate clocks while in stop mode. the def ault state for this option is clear, disabling the oscillator in stop mode. 1 = oscillator enabled during stop mode 0 = oscillator disabled during stop mode (default) scibdsrc ? sci baud rate clock source bit scibdsrc controls the clock source used for the seri al communications interface (sci). the setting of this bit affects the frequency at which the sci operates.see chapter 14 enhanced serial communications interface (esci) module . 1 = internal data bus clock used as clock source for sci (default) 0 = external oscillator used as clock source for sci coprs ? cop rate select bit coprs selects the cop timeout period. reset clears coprs. see chapter 6 computer operating properly (cop) module 1 = cop timeout period = 8176 cgmxclk cycles 0 = cop timeout period = 262,128 cgmxclk cycles lvistop ? lvi enable in stop mode bit when the lvipwrd bit is clear, setting the lvisto p bit enables the lvi to operate during stop mode. reset clears lvistop. 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode lvirstd ? lvi reset disable bit lvirstd disables the reset signal from the lvi module. see chapter 11 low-voltage inhibit (lvi) . 1 = lvi module resets disabled 0 = lvi module resets enabled lvipwrd ? lvi power disable bit lvipwrd disables the lvi module. see chapter 11 low-voltage inhibit (lvi) . 1 = lvi module power disabled 0 = lvi module power enabled address: $001f bit 7654321bit 0 read: coprs lvistop lvirstd lvipwrd lvi5or3 ssrec stop copd write: reset:0000see note000 note: lvi5or3 is only reset via por (power-on reset). figure 5-2. configuration register 1 (config1) configuration register (config) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 94 freescale semiconductor lvi5or3 ? lvi 5-v or 3-v operating mode bit lvi5or3 selects the voltage operating mode of the lvi module (see chapter 11 low-voltage inhibit (lvi) ). the voltage mode selected for the lvi should match the operating v dd (see chapter 21 electrical specifications ) for the lvi?s voltage trip points for each of the modes. 1 = lvi operates in 5-v mode 0 = lvi operates in 3-v mode note the lvi5or3 bit is cleared by a power-on reset (por) only. other resets will leave this bit unaffected. ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096-cgmxclk cycle delay. 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclk cycles note exiting stop mode by any reset will result in the long stop recovery. the short stop recovery delay can be enabled when using a crystal or resonator and the osceninstop bit is set. the short stop recovery delay can be enabled when an external oscillator is used, regardless of the osceninstop setting. the short stop recovery delay must be disabled when the osceninstop bit is clear and a crystal or resonator is used. stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. see chapter 6 computer operating properly (cop) module . 1 = cop module disabled 0 = cop module enabled mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 95 chapter 6 computer operating pr operly (cop) module 6.1 introduction the computer operating properly (cop) module cont ains a free-running counter that generates a reset if allowed to overflow. the cop modul e helps software recover from runaway code. prevent a cop reset by clearing the cop counter periodically. the cop m odule can be disabled through the copd bit in the config register. 6.2 functional description figure 6-1 shows the structure of the cop module. figure 6-1. cop block diagram copctl write cgmxclk reset circuit reset status register internal reset sources 12-bit sim counter clear all stages 6-bit cop counter cop disable reset copctl write clear cop module copen (from sim) cop counter cop clock cop timeout stop instruction (from config) cop rate sel (from config) clear stages 5?12 computer operating properly (cop) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 96 freescale semiconductor the cop counter is a free-running 6-bit counter preceded by the 12-bit sim counter. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 262,128 or 8176 cgmxclk cycles, depending on the state of the cop rate select bit, coprs, in the configuration register. with a 262,128 cgmxclk cycle overflow option, a 4.9152-mhz crystal gives a cop timeout period of 53.3 ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12?5 of the sim counter. note service the cop immediately after rese t and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 cgmxclk cycles and sets the cop bit in the reset status register (rsr). in monitor mode, the cop is disabled if the rst pin or the irq is held at v tst . during the break state, v tst on the rst pin disables the cop. note place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt s ubroutine could keep the cop from generating a reset even while the main program is not working properly. 6.3 i/o signals the following paragraphs describe the signals shown in figure 6-1 . 6.3.1 cgmxclk cgmxclk is the crystal oscillator output signal. cg mxclk frequency is equal to the crystal frequency. 6.3.2 stop instruction the stop instruction clears the sim counter. 6.3.3 copctl write writing any value to the cop control register (c opctl) clears the cop counter and clears stages 12?5 of the sim counter. reading the cop control register returns the low byte of the reset vector. see 6.4 cop control register. 6.3.4 powe r-on reset the power-on reset (por) circuit clears the sim counter 4096 cgmxclk cycles after power-up. 6.3.5 internal reset an internal reset clears the sim counter and the cop counter. cop control register mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 97 6.3.6 copd (cop disable) the copd signal reflects the state of the cop dis able bit (copd) in the configuration register. see chapter 5 configuration register (config). 6.3.7 coprs (cop rate select) the coprs signal reflects the state of the cop rate select bit (coprs) in the configuration register. see chapter 5 configuration register (config). 6.4 cop control register the cop control register (copctl) is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and star ts a new timeout period. reading location $ffff returns the low byte of the reset vector. 6.5 interrupts the cop does not generate central processor unit (cpu) interrupt requests. 6.6 monitor mode when monitor mode is entered with v tst on the irq pin, the cop is disabled as long as v tst remains on the irq pin or the rst pin. when monitor mode is entered by having blank reset vectors and not having v tst on the irq pin, the cop is automatically disabled until a por occurs. 6.7 low-power modes the wait and stop instructions put the microcontroller unit (mcu) in low power-consumption standby modes. 6.7.1 wait mode the cop remains active during wait mode. if cop is enabled, a reset will occur at cop timeout. 6.7.2 stop mode stop mode turns off the cgmxclk input to the cop and clears the sim counter. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 6-2. cop control register (copctl) computer operating properly (cop) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 98 freescale semiconductor to prevent inadvertently turning off the cop with a stop instruction, a configuration option is available that disables the stop instruction. when the stop bit in the configuration register has the stop instruction disabled, execution of a stop in struction results in an illegal opcode reset. 6.8 cop module during break mode the cop is disabled during a break interrupt when v tst is present on the rst pin. mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 99 chapter 7 central processor unit (cpu) 7.1 introduction the m68hc08 cpu (central processor unit) is an e nhanced and fully object-code- compatible version of the m68hc05 cpu. the cpu08 reference manual (document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 7.2 features features of the cpu include: ? object code fully upward-compatible with m68hc05 family ? 16-bit stack pointer with stack manipulation instructions ? 16-bit index register with x-re gister manipulation instructions ? 8-mhz cpu internal bus frequency ? 64-kbyte program/data memory space ? 16 addressing modes ? memory-to-memory data moves without using accumulator ? fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions ? enhanced binary-coded decimal (bcd) data handling ? modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes ? low-power stop and wait modes 7.3 cpu registers figure 7-1 shows the five cpu registers. cpu registers are not part of the memory map. central processor unit (cpu) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 100 freescale semiconductor figure 7-1. cpu registers 7.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. 7.3.2 index register the 16-bit index register allows i ndexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, th e cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. bit 7654321bit 0 read: write: reset: unaffected by reset figure 7-2. accumulator (a) bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 7-3. index register (h:x) accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 cpu registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 101 7.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset a ddressing modes, the stack pointer can function as an index register to access data on t he stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 7.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increm ents to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 7-4. stack pointer (sp) bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 7-5. program counter (pc) central processor unit (cpu) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 102 freescale semiconductor 7.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set per manently to 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. th e daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cp u interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note to maintain m6805 family compatibil ity, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priori ty interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 7-6. condition code register (ccr) arithmetic/logic unit (alu) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 103 z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 7.4 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 7.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 7.5.1 wait mode the wait instruction: ? clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. ? disables the cpu clock 7.5.2 stop mode the stop instruction: ? clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. ? disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 7.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: ? loading the instruction register with the swi instruction ? loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. central processor unit (cpu) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 104 freescale semiconductor 7.7 instruction set summary table 7-1 provides a summary of the m68hc08 instruction set. table 7-1. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 c b0 b7 0 b0 b7 c instruction set summary mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 105 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 table 7-1. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 106 freescale semiconductor clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 table 7-1. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc instruction set summary mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 107 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 table 7-1. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 central processor unit (cpu) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 108 freescale semiconductor pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ? dir 35 dd 4 stop enable interrupts, stop processing, refer to mcu documentation i 0; stop processing ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 7-1. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c opcode map mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 109 7.8 opcode map see table 7-2 . swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 wait enable interrupts; wait for interrupt i bit 0; inhibit cpu clocking until interrupted ??0???inh 8f 1 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit ? not affected table 7-1. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc mc68hc908gz60 ? mc68hc908gz48 ? mc68h c908gz32 data sheet, rev. 6 110 freescale semiconductor central processor unit (cpu) table 7-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 111 chapter 8 external interrupt (irq) 8.1 introduction the irq (external interrupt) module provides a maskable interrupt input. 8.2 features features of the irq module include: ? a dedicated external interrupt pin (irq ) ? irq interrupt control bits ? hysteresis buffer ? programmable edge-only or edge and level interrupt sensitivity ? automatic interrupt acknowledge ? internal pullup resistor 8.3 functional description a low applied to the external interrupt pin can la tch a central processor unit (cpu) interrupt request. figure 8-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until one of the following actions occurs: ? vector fetch ? a vector fetch automatically gener ates an interrupt acknowledge signal that clears the latch that caused the vector fetch. ? software clear ? software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (intscr). writing a 1 to the ack bit clears the irq latch. ? reset ? a reset automatically clears the interrupt latch. the external interrupt pin is falling-edge triggered out of reset and is software-configurable to be either falling-edge or falling-edge and low-level triggered. th e mode bit in the intscr controls the triggering sensitivity of the irq pin. when an interrupt pin is edge-triggered only (mode = 0), the interrupt remains set until a vector fetch, software clear, or reset occurs. external interrupt (irq) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 112 freescale semiconductor figure 8-1. irq module block diagram when an interrupt pin is both falling-edge and low-level triggered (mode = 1), the interrupt remains set until both of these events occur: ? vector fetch or software clear ? return of the interrupt pin to a high level the vector fetch or software clear may occur before or after the interrupt pin returns to a high level. as long as the pin is low, the interrupt request remain s pending. a reset will clear the latch and the mode control bit, thereby clearing the in terrupt even if the pin stays low. when set, the imask bit in the intscr masks all external interrupt requests. a latched interrupt request is not presented to the interrupt priori ty logic unless the imask bit is clear. note the interrupt mask (i) in the condi tion code register (ccr) masks all interrupt requests, including external interrupt requests. addr.register name bit 7654321bit 0 $001d irq status and control register (intscr) see page 114. read:0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 8-2. irq i/o register summary imask dq ck clr irq high interrupt to mode select logic request v dd mode voltage detect irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd internal pullup device ack irq synchronizer irq pin mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 113 8.4 irq pin a falling edge on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode bit is set, the irq pin is both falling-edge-sensitive a nd low-level-sensitive. with mode set, both of the following actions must occur to clear irq: ? vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a 1 to the ack bit in the interrupt status and control register (intscr). t he ack bit is useful in applications that poll the irq pin and require software to clear the irq latch. writing to the ack bit prior to leaving an interrupt service routine can also prevent spur ious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bit latches another interrupt request. if the irq mask bit, imask, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. ? return of the irq pin to a high level ? as long as the irq pin is low, irq remains active. the vector fetch or software clear and the return of the irq pin to a high level may occur in any order. the interrupt request remains pending as long as the irq pin is low. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge-sensitive only. with mode clear, a vector fetch or software clear immediately clears the irq latch. the irqf bit in the intscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it usef ul in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq pin. note when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. 8.5 irq module duri ng break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear the latch during the break state. see chapter 20 development support . to allow software to clear the irq latch during a break interrupt, write a 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect cpu interrupt flags during the break state, wr ite a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq interrupt flags. external interrupt (irq) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 114 freescale semiconductor 8.6 irq status and control register the irq status and control register (intscr) contro ls and monitors operation of the irq module. the intscr: ? shows the state of the irq flag ? clears the irq latch ? masks irq interrupt request ? controls triggering sensitivity of the irq interrupt pin irqf ? irq flag bit this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a 1 to this write-only bit clears the irq latch. ack always reads as 0. reset clears ack. imask ? irq interrupt mask bit writing a 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only address: $001d bit 7654321bit 0 read:0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 8-3. irq status and control register (intscr) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 115 chapter 9 keyboard interrupt module (kbi) 9.1 introduction the keyboard interrupt module (kbi) provides eight independently maskable external interrupts which are accessible via pta0?pta7. when a port pin is e nabled for keyboard interrupt function, an internal pullup/pulldown device is also enabled on the pin. 9.2 features features include: ? eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask ? hysteresis buffers ? programmable edge-only or edge- and level- interrupt sensitivity ? edge detect programmable for rising or falling edges ? level detect programmable for high or low levels ? exit from low-power modes ? pullup/pulldown device automatic ally configured based on polarity of edge/level selection 9.3 functional description writing to the kbie7?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pi n. enabling a keyboard interrupt pin also enables its internal pullup/pulldown device. on falling edge or low level selection a pullup device is configured. on rising edge or high level selecti on a pulldown device is configured. ? a falling edge is detected when an enabled keyboa rd input signal is seen as a 1 (the deasserted level) during one bus cycle and then a 0 (the asserted level) during the next cycle. ? a rising edge is detected when the input signal is seen as a 0 during one bus cycle and then a 1 during the next cycle. a keyboard interrupt is latched when one or more keyboard pins are asserted. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. keyboard interrupt module (kbi) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 116 freescale semiconductor figure 9-1. block diagram highlighting kbi block and pins single breakpoint break module system integration module programmable timebase module monitor mode entry serial peripheral 6-channel timer interface module dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash ? 62,078 bytes user ram ? 2048 bytes monitor rom user flash vector space ? 52 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 rst (1) irq (1) interface module interrupt module computer operating properly module pta7/kbd7/ad15? 10-bit analog-to-digital converter module ptc6 (2) ptc5 (2) ptc4 (2, 3) ptc3 (2, 3) ptc2 (2, 3) ptc1/can rx (2, 3) ptc0/can tx (2, 3) ptd7/t2ch1 (2) ptd6/t2ch0 (2) ptd5/t1ch1 (2) ptd4/t1ch0 (2) ptd3/spsck (2) ptd2/mosi (2) ptd1/miso (2) ptd0/ss /mclk (2) pte1/rxd pte0/txd 2-channel timer interface module enhanced serial interface module security module power-on reset module memory map module configuration register 1?2 module power v ss v dd v ssa v dda 1. pin contains in tegrated pullup device. 2. ports are software configurable with pullup device if input port or pullup/pulldown device for keyboard input. 3. higher current drive port pins v ddad /v refh v ssad /v refl pte5?pte2 communications clock generator module cgmxfc phase locked loop 1?8 mhz oscillator portb ddrb ptb7/ad7? portf ddrf ptf7/t2ch5 module portg ddrg ptg7/ad23? ptf6/t2ch4 ptf5/t2ch3 ptf4/t2ch2 ptf3?pft0 (3) mscan module pta0/kbd0/ad8 (2) ptb0/ad0 ptg0/ad16 functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 117 the kbip7?kbip0 bits determine the polarity of the keyboard pin detection. these bits along with the modek bit determine whether a logic level (0 or 1) and/or a falling (or rising) edge is being detected. ? if the keyboard interrupt is edge-sensitive only, a falling (or rising) edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already asserted. to prevent losing an interrupt request on one pin because another pin is still assert ed, software can disable the latter pin while it is asserted. ? if the keyboard interrupt is edge and level sensitiv e, an interrupt request is present as long as any keyboard interrupt pin is asserted and the pin is keyboard interrupt enabled. figure 9-2. keyboard module block diagram addr.register name bit 7654321bit 0 $001a keyboard status and control register (intkbscr) see page 120. read:0000 keyf 0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (intkbier) see page 121. read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $0448 keyboard interrupt polarity register (intkbipr) see page 121. read: kbip7 kbip6 kbip5 kbip4 kbip3 kbip2 kbip1 kbip0 write: reset:00000000 = unimplemented figure 9-3. i/o register summary keyboard interrupt request vector fetch decoder ackk internal bus reset kbie0 kbd0 0 1 s kbip0 kbie7 kbd7 0 1 s kbip7 dq ck clr v dd modek imaskk synchronizer keyf to pullup/ to pullup/ pulldown enable pulldown enable keyboard interrupt module (kbi) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 118 freescale semiconductor if the modek bit is set and depending on the kbipx bit, the keyboard interrupt pins are both falling (or rising) edge and low (or high) level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: ? vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowledge signal by writing a 1 to the ackk bit in the keyboard status and control regi ster (intkbscr). the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling (or rising) edge that occurs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $ffe0 and $ffe1. ? return of all enabled keyboard interrupt pins to 1 (or 0) ? as long as any enabled keyboard interrupt pin is 0 (or 1), the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to 1 (or 0) may occur in any order. if the modek bit is clear and depending on the kbipx bit, the keyboard interrupt pin is falling (or rising) edge sensitive only. with modek clear, a vector fetc h or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the mo dek bit, clearing the interrupt request even if a keyboard interrupt pin stays at 0 (or 1). the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by t he keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. note setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a 0 for software to read the pin. 9.4 keyboard initialization when a keyboard interrupt pin is enabled, it takes time for the internal pullup/pulldown device to reach a 1 (or 0). therefore, a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins and polarity by setting the appropriate kbiex bits in the keyboard interrupt enable register and the kbipx bits in the keyboard interrupt polarity register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. low-power modes mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 119 an interrupt signal on an edge-triggered pin can be acknowledged immediately a fter enabling the pin. an interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setti ng the appropriate ddra bits in data direction register a. 2. write 1s (or 0s) to the appropriate port a data register bits. 3. enable the kbi pins and polarity by setting the appropriate kbiex bits in the keyboard interrupt enable register and the kbipx bits in the keyboard interrupt polarity register. 9.5 low-power modes the wait and stop instructions put the microcontroller unit (mcu) in low power-consumption standby modes. 9.5.1 wait mode the keyboard module remains active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 9.5.2 stop mode the keyboard module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 9.6 keyboard module during break interrupts the system integration module (sim) controls whet her the keyboard interrupt latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. to allow software to clear the keyboard interrupt latch during a break interrupt, write a 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the keyboard acknowledge bit (ackk) in t he keyboard status and control register during the break state has no effect. see 9.7.1 keyboard status and control register . 9.7 i/o registers these registers control and monitor operation of the keyboard module: ? keyboard status and control register (intkbscr) ? keyboard interrupt enable register (intkbier) ? keyboard interrupt polarity register (intkbipr) keyboard interrupt module (kbi) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 120 freescale semiconductor 9.7.1 keyboard status and contro l register the keyboard status and control register: ? flags keyboard interrupt requests ? acknowledges keyboard interrupt requests ? masks keyboard interrupt requests ? controls keyboard interrupt triggering sensitivity bits 7?4 ? not used these read-only bits always read as 0s. keyf ? keyboard flag bit this read-only bit is set when a keyboard inte rrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a 1 to this write-only bit clears the keyboard interrupt request. ackk always reads as 0. reset clears ackk. imaskk ? keyboard interrupt mask bit writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt requests on edge and level detect 0 = keyboard interrupt requests on edges only address: $001a bit 7654321bit 0 read:0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 9-4. keyboard status and control register (intkbscr) i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 121 9.7.2 keyboard inte rrupt enable register the keyboard interrupt enable register enables or disables each port a pin to operate as a keyboard interrupt pin. kbie7?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corre sponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = ptax pin enabled as keyboard interrupt pin 0 = ptax pin not enabled as keyboard interrupt pin 9.7.3 keyboard interr upt polarity register the kbip7?kbip0 bits determine the polarity of the keyboard pin detection. these bits along with the modek bit determine whether a logic level (0 or 1) and/or a falling (or rising) edge is being detected. the kbipx bits also select the pullup re sistor (kbipx = 0) or pulldown resistor (kbipx = 1) for each enabled keyboard interrupt pin. kbip7?kbip0 ? keyboard interrupt polarity bits each of these read/write bits enables the polarity of the keyboard interrupt pin. reset clears the keyboard interrupt polarity register. 1 = keyboard polarity is rising edge and/or high level 0 = keyboard polarity is falling edge and/or low level address: $001b bit 7654321bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 9-5. keyboard interrupt enable register (intkbier) address: $0448 bit 7654321bit 0 read: kbip7 kbip6 kbip5 kbip4 kbip3 kbip2 kbip1 kbip0 write: reset:00000000 figure 9-6. keyboard interrupt polarity register (intkbipr) keyboard interrupt module (kbi) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 122 freescale semiconductor mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 123 chapter 10 low-power modes 10.1 introduction the microcontroller (mcu) may enter two low-pow er modes: wait mode and stop mode. they are common to all hc08 mcus and are entered through in struction execution. this section describes how each module acts in the low-power modes. 10.1.1 wait mode the wait instruction puts the mcu in a low-power standby mode in which the central processor unit (cpu) clock is disabled but the bus clock continues to run. power consumption can be further reduced by disabling the low-voltage inhibit (lvi) module through bits in the config1 register. see chapter 5 configuration register (config) . 10.1.2 stop mode stop mode is entered when a stop instruction is ex ecuted. the cpu clock is disabled and the bus clock is disabled if the osceninstop bit in the config2 register is a 0. see chapter 5 configuration register (config) . 10.2 analog-to-digi tal converter (adc) 10.2.1 wait mode the analog-to-digital converter (adc) continues normal operation during wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting adch4?adch0 bits in the adc status and control register before executing the wait instruction. 10.2.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode after an external interrupt. allow one conversion cycle to stabi lize the analog circuitry. low-power modes mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 124 freescale semiconductor 10.3 break module (brk) 10.3.1 wait mode the break (brk) module is active in wait mode. in th e break routine, the user can subtract one from the return address on the stack if the sbsw bit in the break status register is set. 10.3.2 stop mode the break module is inactive in stop mode. the stop instruction does not affect break module register states. 10.4 central pro cessor unit (cpu) 10.4.1 wait mode the wait instruction: ? clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. ? disables the cpu clock 10.4.2 stop mode the stop instruction: ? clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. ? disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 10.5 clock generator module (cgm) 10.5.1 wait mode the clock generator module (cgm) remains active in wait mode. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake the mcu from wait mode also can deselect the pll output without turning off the pll. 10.5.2 stop mode if the osceninstop bit in the config2 register is cl eared (default), then the stop instruction disables the cgm (oscillator and phase-locked loop) and hold s low all cgm outputs (cgmxclk, cgmout, and cgmint). if the osceninstop bit in the config2 register is se t, then the phase locked loop is shut off, but the oscillator will continue to operate in stop mode. computer operating properly module (cop) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 125 10.6 computer operatin g properly module (cop) 10.6.1 wait mode the cop remains active during wait mode. if cop is enabled, a reset will occur at cop timeout. 10.6.2 stop mode stop mode turns off the cgmxclk input to the cop and clears the sim counter. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. the stop bit in the config1 register enables the stop instruction. to prevent inadvertently turning off the cop with a stop instruction, disable the stop instruction by clearing the stop bit. 10.7 external inte rrupt module (irq) 10.7.1 wait mode the external interrupt (irq ) module remains active in wait mode. clearing the imask bit in the irq status and control register enables irq cpu interrupt requests to bring the mcu out of wait mode. 10.7.2 stop mode the irq module remains active in stop mode. clearing the imask bit in the irq status and control register enables irq cpu interrupt requests to bring the mcu out of stop mode. 10.8 keyboard inte rrupt module (kbi) 10.8.1 wait mode the keyboard interrupt (kbi) modul e remains active in wait mode . clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 10.8.2 stop mode the keyboard module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. low-power modes mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 126 freescale semiconductor 10.9 low-voltage inhibit module (lvi) 10.9.1 wait mode if enabled, the low-voltage inhibit (lvi) module remains active in wait mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 10.9.2 stop mode if enabled, the lvi module remains active in st op mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. 10.10 enhanced serial communic ations interface module (esci) 10.10.1 wait mode the enhanced serial communications interface (esci), or sci module for short, module remains active in wait mode. any enabled cpu interrupt request fr om the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. 10.10.2 stop mode the sci module is inactive in stop mode. the stop in struction does not affect sci register states. sci module operation resumes after the mcu exits stop mode. because the internal clock is inactive during st op mode, entering stop mode during an sci transmission or reception results in invalid data. 10.11 serial peripheral interface module (spi) 10.11.1 wait mode the serial peripheral interface (spi) module remains active in wait mode. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. 10.11.2 stop mode the spi module is inactive in stop mode. the stop instruction does not affect spi register states. spi operation resumes after an external interrupt. if stop mode is exited by reset, any transfer in progress is aborted, and the spi is reset. timer interface modu le (tim1 and tim2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 127 10.12 timer interface module (tim1 and tim2) 10.12.1 wait mode the timer interface modules (tim) remain active in wait mode. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, r educe power consumption by stopping the tim before executing the wait instruction. 10.12.2 stop mode the tim is inactive in stop mode. the stop instruction does not affect register states or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 10.13 timebase module (tbm) 10.13.1 wait mode the timebase module (tbm) remains active after execut ion of the wait instruction. in wait mode, the timebase register is not accessible by the cpu. if the timebase functions are not required during wa it mode, reduce the power consumption by stopping the timebase before enabling the wait instruction. 10.13.2 stop mode the timebase module may remain active after execution of the stop instruction if the oscillator has been enabled to operate during stop mode through the osceninstop bit in the config2 register. the timebase module can be used in this mode to generate a periodic wakeup from stop mode. if the oscillator has not been enabled to operate in stop mode, the timebase module will not be active during stop mode. in stop mode, the timebase r egister is not accessible by the cpu. if the timebase functions are not required during st op mode, reduce the power consumption by stopping the timebase before enabling the stop instruction. 10.14 scalable controller area network module (mscan) 10.14.1 wait mode the scalable controller area network (mscan) modul e remains active after execution of the wait instruction. in wait mode, the mscan08 registers are not accessible by the cpu. if the mscan08 functions are not required during wait mode, reduce the power co nsumption by disabling the mscan08 module before enabling the wait instruction. 10.14.2 stop mode the mscan08 module is inactive in stop mode. the st op instruction does not affect mscan08 register states. because the internal clock is inactive duri ng stop mode, entering stop mode during an mscan08 transmission or reception results in invalid data. low-power modes mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 128 freescale semiconductor 10.15 exiting wait mode these events restart the cpu clock and load the program counter with the reset vector or with an interrupt vector: ? external reset ? a low on the rst pin resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. ? external interrupt ? a high-to-low trans ition on an external interrupt pin (irq pin) loads the program counter with the contents of locations: $fffa and $fffb; irq pin. ? break interrupt ? in emulation mode, a break inte rrupt loads the program counter with the contents of $fffc and $fffd. ? computer operating properly (cop) module reset ? a timeout of the cop counter resets the mcu and loads the program counter with the contents of $fffe and $ffff. ? low-voltage inhibit (lvi) module reset ? a power supply voltage below the v tripf voltage resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. ? clock generator module (cgm) interrupt ? a cpu interrupt request from the cgm loads the program counter with the contents of $fff8 and $fff9. ? keyboard interrupt (kbi) module ? a cpu inte rrupt request from the kbi module loads the program counter with the contents of $ffe0 and $ffe1. ? timer 1 interface (tim1) module interrupt ? a cpu interrupt request from the tim1 loads the program counter with the contents of: ? $fff2 and $fff3; tim1 overflow ? $fff4 and $fff5; tim1 channel 1 ? $fff6 and $fff7; tim1 channel 0 ? timer 2 interface module (tim2) interrupt ? a cpu interrupt request from the tim2 loads the program counter with the contents of: ? $ffec and $ffed; tim2 overflow ? $ffee and $ffef; tim2 channel 1 ? $fff0 and $fff1; tim2 channel 0 ? $ffcc and $ffcd; tim2 channel 5 ? $ffce and $ffcf; tim2 channel 4 ? $ffd0 and $ffd1; tim2 channel 3 ? $ffd2 and $ffd3; tim2 channel 2 ? serial peripheral interface (spi) module interrupt ? a cpu interrupt request from the spi loads the program counter with the contents of: ? $ffe8 and $ffe9; spi transmitter ? $ffea and $ffeb; spi receiver ? serial communications interface (sci) module in terrupt ? a cpu interrupt request from the sci loads the program counter with the contents of: ? $ffe2 and $ffe3; sci transmitter ? $ffe4 and $ffe5; sci receiver ? $ffe6 and $ffe7; sci receiver error ? analog-to-digital converter (adc) module interrupt ? a cpu interrupt request from the adc loads the program counter with the contents of: $ffde and $ffdf; adc conversion complete. ? timebase module (tbm) interrupt ? a cpu interru pt request from the tbm loads the program counter with the contents of: $ffdc and $ffdd; tbm interrupt. exiting stop mode mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 129 ? mscan module interrupt ? a cpu interrupt request from the mscan08 loads the program counter with the contents of: ? $ffd4 and $ffd5; mscan08 transmitter ? $ffd6 and $ffd7; mscan08 receiver ? $ffd8 and $ffd9; mscan08 error ? $ffda and $ffdb; mscan08 wakeup 10.16 exiting stop mode these events restart the system clocks and load the program counter with the reset vector or with an interrupt vector: ? external reset ? a low on the rst pin resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. ? external interrupt ? a high-to-low transition on an external interrupt pin loads the program counter with the contents of locations: ? $fffa and $fffb; irq pin ? $ffe0 and $ffe1; keyboard interrupt pins (low-to-high transition when kbipx bits are set) ? low-voltage inhibit (lvi) reset ? a power supply voltage below the v tripf voltage resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. ? break interrupt ? in emulation mode, a break inte rrupt loads the program counter with the contents of locations $fffc and $fffd. ? timebase module (tbm) interrupt ? a tbm interrupt loads the program counter with the contents of locations $ffdc and $ffdd when the timebase counter has rolled over. this allows the tbm to generate a periodic wakeup from stop mode. ? mscan08 interrupt ? mscan08 bus activity can wake the mcu from cpu stop. however, until the oscillator starts up and synchronization is ac hieved the mscan08 will not respond to incoming data. upon exit from stop mode, the system clocks begin running after an o scillator stabilization delay. a 12-bit stop recovery counter inhibits the system clocks fo r 4096 cgmxclk cycles after the reset or external interrupt. the short stop recovery bit, ssrec, in the config1 register controls the oscillator stabilization delay during stop recovery. setting ssrec reduces stop recovery time from 4096 cgmxclk cycles to 32 cgmxclk cycles. note use the full stop recovery time (ssrec = 0) in applications that use an external crystal unless the osceninstop bit is set. low-power modes mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 130 freescale semiconductor mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 131 chapter 11 low-voltage inhibit (lvi) 11.1 introduction this section describes the low-voltage inhibit (lvi) module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls below the lvi trip falling voltage, v tripf . 11.2 features features of the lvi module include: ? programmable lvi reset ? selectable lvi trip voltage ? programmable stop mode operation 11.3 functional description figure 11-1 shows the structure of the lvi module. the lvi is enabled out of reset. the lvi module contains a bandgap reference circuit and comparator . clearing the lvi power disable bit, lvipwrd, enables the lvi to monitor v dd voltage. clearing the lvi reset disable bit, lvirstd, enables the lvi module to generate a reset when v dd falls below a voltage, v tripf . setting the lvi enable in stop mode bit, lvistop, enables the lvi to operate in stop mode. se tting the lvi 5-v or 3-v trip point bit, lvi5or3, enables the trip point voltage, v tripf , to be configured for 5-v operation. clearing the lvi5or3 bit enables the trip point voltage, v tripf , to be configured for 3-v operation. the actual trip points are shown in chapter 21 electrical specifications . note after a power-on reset (por) the lvi?s default mode of operation is 3 v. if a 5-v system is used, the user must set the lvi5or3 bit to raise the trip point to 5-v operation. note that this must be done after every power-on reset since the default will revert back to 3-v mode after each power-on reset. if the v dd supply is below the 5-v mode trip voltage but above the 3-v mode trip voltage when por is re leased, the part will operate because v tripf defaults to 3-v mode after a por. so, in a 5-v system care must be taken to ensure that v dd is above the 5-v mode trip voltage after por is released. if the user requires 5-v mode and sets the lvi5or3 bit after a power-on reset while the v dd supply is not above the v tripr for 5-v mode, the microcontroller unit (mcu) will immediatel y go into reset. the lvi in this case will hold the part in reset until either v dd goes above the rising 5-v trip point, v tripr , which will release reset or v dd decreases to approximately 0 v which will re-trigger the power-on reset and reset the trip point to 3-v operation. low-voltage inhibit (lvi) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 132 freescale semiconductor lvistop, lvipwrd, lvi5or3, and lvirstd are in the configuration register (config1). see figure 5-2. configurati on register 1 (config1) for details of the lvi?s c onfiguration bits. once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, v tripr , which causes the mcu to exit reset. see 15.3.2.5 low-voltage inhibit (lvi) reset for details of the interaction between the sim and the lvi. the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. figure 11-1. lvi module block diagram 11.3.1 polled lvi operation in applications that can operate at v dd levels below the v tripf level, software can monitor v dd by polling the lviout bit. in the configuration register, the lvipwrd bit must be 0 to enable the lvi module, and the lvirstd bit must be 1 to disable lvi resets. 11.3.2 forced reset operation in applications that require v dd to remain above the v tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls below the v tripf level. in the configuration register, the lvipwrd and lvirstd bits must be cleared to enable the lvi module and to enable lvi resets. addr.register name bit 7654321bit 0 $fe0c lvi status register (lvisr) see page 133. read:lviout0000000 write: reset:00000000 = unimplemented figure 11-2. lvi i/o register summary low v dd detector lvipwrd stop instruction lvistop lvi reset lviout v dd > lvi trip = 0 v dd lvi trip = 1 from config from config1 v dd from config1 lvirstd lvi5or3 from config1 lvi status register mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 133 11.3.3 voltage hyst eresis protection once the lvi has triggered (by having v dd fall below v tripf ), the lvi will maintain a reset condition until v dd rises above the rising trip point voltage, v tripr . this prevents a condition in which the mcu is continually entering and exiting reset if v dd is approximately equal to v tripf . v tripr is greater than v tripf by the hysteresis voltage, v hys . 11.3.4 lvi trip selection the lvi5or3 bit in the configuration register selects whether the lvi is configured for 5-v or 3-v protection. note the microcontroller is guaranteed to operate at a minimum supply voltage. the trip point (v tripf [5 v] or v tripf [3 v]) may be lower than this. see chapter 21 electrical specifications for the actual trip point voltages. 11.4 lvi status register the lvi status register (lvisr) indicates if the v dd voltage was detected below the v tripf level. lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the v tripf trip voltage (see table 11-1 ). reset clears the lviout bit. 11.5 lvi interrupts the lvi module does not generate interrupt requests. address: $fe0c bit 7654321bit 0 read:lviout0000000 write: reset:00000000 = unimplemented figure 11-3. lvi status register (lvisr) table 11-1. lviout bit indication v dd lviout v dd > v tripr 0 v dd < v tripf 1 v tripf < v dd < v tripr previous value low-voltage inhibit (lvi) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 134 freescale semiconductor 11.6 low-power modes the stop and wait instructions put the mcu in low power-consumption standby modes. 11.6.1 wait mode if enabled, the lvi module remains active in wait m ode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 11.6.2 stop mode if enabled in stop mode (lvistop bit in the configuration register is set), the lvi module remains active in stop mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 135 chapter 12 mscan08 controller (mscan08) 12.1 introduction the mscan08 is the specific implementation of the scalable controller area network (mscan) concept targeted for the m68hc08 microcontroller family. the module is a communication controller implement ing the can 2.0 a/b protocol as defined in the bosch specification dated september, 1991. the can protocol was primarily, but not exclusivel y, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the electromagnetic interference (emi) environment of a v ehicle, cost-effectiveness, and required bandwidth. mscan08 utilizes an advanced buffer arrangement, resu lting in a predictable real-time behavior, and simplifies the application software. 12.2 features basic features of the mscan08 are: ? mscan08 enable is software controlled by bit (m scanen) in configuration register (config2) ? modular architecture ? implementation of the can protocol ? version 2.0a/b ? standard and extended data frames ? 0?8 bytes data length. ? programmable bit rate up to 1 mbps depending on the actual bit timing and the clock jitter of the phase-locked loop (pll) ? support for remote frames ? double-buffered receive storage scheme ? triple-buffered transmit storage scheme with intern al prioritization using a ?local priority? concept ? flexible maskable identifier filter supports alternatively one full size extended identifier filter or two 16-bit filters or four 8-bit filters ? programmable wakeup functionality with integrated low-pass filter ? programmable loop-back mode supports self-test operation ? separate signalling and interrupt capabilities for al l can receiver and transmitter error states (warning, error passive, bus off) ? programmable mscan08 clock source either cpu bus clock or crystal oscillator output ? programmable link to timer interface module 1 channel 0 for time-stamping and network synchronization ? low-power sleep mode mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 136 freescale semiconductor figure 12-1. block diagram highlighting mscan08 block and pins single breakpoint break module system integration module programmable timebase module monitor mode entry serial peripheral 6-channel timer interface module dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash ? 62,078 bytes user ram ? 2048 bytes monitor rom user flash vector space ? 52 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 rst (1) irq (1) interface module interrupt module computer operating properly module pta7/kbd7/ad15? 10-bit analog-to-digital converter module ptc6 (2) ptc5 (2) ptc4 (2, 3) ptc3 (2, 3) ptc2 (2, 3) ptc1/can rx (2, 3) ptc0/can tx (2, 3) ptd7/t2ch1 (2) ptd6/t2ch0 (2) ptd5/t1ch1 (2) ptd4/t1ch0 (2) ptd3/spsck (2) ptd2/mosi (2) ptd1/miso (2) ptd0/ss /mclk (2) pte1/rxd pte0/txd 2-channel timer interface module enhanced serial interface module security module power-on reset module memory map module configuration register 1?2 module power v ss v dd v ssa v dda 1. pin contains in tegrated pullup device. 2. ports are software configurable with pullup device if input port or pullup/pulldown device for keyboard input. 3. higher current drive port pins v ddad /v refh v ssad /v refl pte5?pte2 communications clock generator module cgmxfc phase locked loop 1?8 mhz oscillator portb ddrb ptb7/ad7? portf ddrf ptf7/t2ch5 module portg ddrg ptg7/ad23? ptf6/t2ch4 ptf5/t2ch3 ptf4/t2ch2 ptf3?pft0 (3) mscan module pta0/kbd0/ad8 (2) ptb0/ad0 ptg0/ad16 external pins mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 137 12.3 external pins the mscan08 uses two external pins, one input (can rx ) and one output (can tx ). the can tx output pin represents the logic level on the can: 0 is fo r a dominant state, and 1 is for a recessive state. a typical can system with mscan08 is shown in figure 12-2 . figure 12-2. the can system each can station is connected physically to th e can bus lines through a transceiver chip. the transceiver is capable of driving the large current needed for the can and has current protection against defected can or defected stations. 12.4 message storage mscan08 facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 12.4.1 background modern application layer software is bui lt under two fundamental assumptions: 1. any can node is able to send out a stream of scheduled messages without releasing the bus between two messages. such nodes will arbitrate for the bus right after sending the previous message and will only release the bu s in case of lost arbitration. 2. the internal message queue within any can node is organized as such that the highest priority message will be sent out first if more than one message is ready to be sent. above behavior cannot be achieved with a single transmi t buffer. that buffer must be reloaded right after the previous message has been sent. this loading proc ess lasts a definite amount of time and has to be c a n bus can controller (mscan08) transceiver can node 1 can station 1 can node 2 can node n can_l can_h can tx can rx mcu mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 138 freescale semiconductor completed within the inter-frame sequence (ifs) to be able to send an uninterrupted stream of messages. even if this is feasible for limited can bus speeds, it requires that the cpu reacts with short latencies to the transmit interrupt. a double buffer scheme would de-couple the re-loading of the transmit buffers from the actual message being sent and as such reduces the reactiveness requirements on the cpu. problems may arise if the sending of a message would be finished just while t he cpu re-loads the second buffer. in that case, no buffer would then be ready for transmi ssion and the bus would be released. at least three transmit buffers are required to meet the first of the above requirements under all circumstances. the mscan08 has three transmit buffers. the second requirement calls for some sort of inte rnal prioritization which the mscan08 implements with the ?local priority? concept described in 12.4.2 receive structures . 12.4.2 receive structures the received messages are stored in a 2-stage input first in first out (fifo). the two message buffers are mapped using a "ping pong" arrangement into a single memory area (see figure 12-3 ). while the background receive buffer (rxbg) is exclusively asso ciated to the mscan08, the foreground receive buffer (rxfg) is addressable by the central proce ssor unit (cpu08). this scheme simplifies the handler software, because only one address area is applicable for the receive process. both buffers have a size of 13 bytes to store the ca n control bits, the identifier (standard or extended), and the data content. for details, see 12.12 programmer?s model of message storage . the receiver full flag (rxf) in the mscan08 receiver flag register (crflg), signals the status of the foreground receive buffer. when the buffer contains a correctly received message with matching identifier, this flag is set. see 12.13.5 mscan08 receiver flag register (crflg) on reception, each message is checked to see if it passes the filter (for details see 12.5 identifier acceptance filter ) and in parallel is written into rxbg. the mscan08 copies the content of rxbg into rxfg (1) , sets the rxf flag, and generates a receive interrupt to the cpu (2) . the user?s receive handler has to read the received message from rxfg and to re set the rxf flag to acknowledge the interrupt and to release the foreground buffer. a new message which can follow immediately af ter the ifs field of the can frame, is received into rxbg. the overwr iting of the background buffer is independent of the identifier filter function. when the mscan08 module is transmitting, the mscan08 receives its own messages into the background receive buffer, rxbg. it does not over write rxfg, generate a receive interrupt or acknowledge its own messages on the can bus. the ex ception to this rule is in loop-back mode (see 12.13.2 mscan08 module control register 1 ), where the mscan08 treats its own messages exactly like all other incoming messages. the mscan08 receives its own transmitted messages in the event that it loses arbitration. if arbitration is lost, the mscan08 must be prepared to become the receiver. an overrun condition occurs when both the for eground and the background receive message buffers are filled with correctly received messages with acc epted identifiers and another message is correctly received from the bus with an accepted identifi er. the latter message will be discarded and an error interrupt with overrun indication will be generated if enabled. the mscan08 is still able to transmit messages with both receive message buffers f illed, but all incoming messages are discarded. 1. only if the rxf flag is not set. 2. the receive interrupt will occur only if not masked. a polling scheme can be applied on rxf also. message storage mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 139 figure 12-3. user model for message buffer organization 12.4.3 transmit structures the mscan08 has a triple transmit buffer scheme to allow multiple messages to be set up in advance and to achieve an optimized real-time performance. the three buffers are arranged as shown in figure 12-3 . all three buffers have a 13-byte data structure si milar to the outline of the receive buffers (see 12.12 programmer?s model of message storage ). an additional transmit buffer priority register (tbpr) contains an 8-bit ?local pr iority? field (prio) (see 12.12.5 transmit buffer priority registers ). rxfg rxbg tx0 rxf txe prio tx1 txe prio tx2 txe prio mscan08 cpu08 i bus mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 140 freescale semiconductor to transmit a message, the cpu08 has to identify an av ailable transmit buffer which is indicated by a set transmit buffer empty (txe) flag in the ms can08 transmitter flag register (ctflg) (see 12.13.7 mscan08 transmitter flag register ). the cpu08 then stores the identifier, the control bits and the data content into one of the transmit buffers. finally, the buffer has to be flagged ready for transmission by clearing the txe flag. the mscan08 then will schedule the message for transmission and will signal the successful transmission of the buffer by setting the txe flag. a transmit interrupt is generated (1) when txe is set and can be used to drive the application software to re-load the buffer. in case more than one buffer is scheduled for trans mission when the can bus becomes available for arbitration, the mscan08 uses the local priority setti ng of the three buffers for prioritization. for this purpose, every transmit buffer has an 8-bit local prio rity field (prio). the application software sets this field when the message is set up. the local priority refl ects the priority of this particular message relative to the set of messages being emitted from this node. th e lowest binary value of the prio field is defined as the highest priority. the internal scheduling process takes place whenever th e mscan08 arbitrates for the bus. this is also the case after the occurrence of a transmission error. when a high priority message is scheduled by the appl ication software, it may become necessary to abort a lower priority message being set up in one of the th ree transmit buffers. as messages that are already under transmission cannot be aborted, the user ha s to request the abort by setting the corresponding abort request flag (abtrq) in the transmission contro l register (ctcr). the mscan08 will then grant the request, if possible, by setting the corresponding abort request acknowledge (abtak) and the txe flag in order to release the buffer and by generating a transmit interrupt. the transmit interrupt handler software can tell from the setting of the abtak flag whether the message was actually aborted (abtak = 1) or sent (abtak = 0). 12.5 identifier acceptance filter the identifier acceptance registers (cidar0?cidar3) define the acceptance patterns of the standard or extended identifier (id10?id0 or id28?id0). any of t hese bits can be marked ?don?t care? in the identifier mask registers (cidmr0?cidmr3). a filter hit is indicated to the application on so ftware by a set rxf (receive buffer full flag, see 12.13.5 mscan08 receiver flag register (crflg) ) and two bits in the identifier acceptance control register (see 12.13.9 mscan08 identifier acceptance control register ). these identifier hit flags (idhit1 and idhit0) clearly identify the filter section that caused the acce ptance. they simplify the application software?s task to identify the cause of the receiver interrupt. in case that more than one hit occurs (two or more filters match) the lower hit has priority. a very flexible programmable generic identifier acceptance filter has be en introduced to reduce the cpu interrupt loading. the filter is programmable to operate in four different modes: 1. single identifier acceptance filter , each to be applied to a) the full 29 bits of the extended identifier and to the following bits of the can frame: rtr, ide, srr or b) the 11 bits of the standard identifier plus the rtr and ide bits of can 2.0a/b messages. this mode implements a single filter for a full length can 2.0b compliant extended identifier. figure 12-4 shows how the 32-bit filter bank (cidar0-3, cidmr0-3) produces a filter 0 hit. 1. the transmit interrupt will occur only if not ma sked. a polling scheme can be applied on txe also. identifier acceptance filter mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 141 2. two identifier acceptance filt ers, each to be applied to: a. the 14 most significant bits of the extended identifier plus the srr and the ide bits of can2.0b messages, or b. the 11 bits of the identifier plus the rtr and ide bits of can 2.0a/b messages. figure 12-5 shows how the 32-bit filter bank (cid ar0?cidar3 and cidmr0?cidmr3) produces filter 0 and 1 hits. 3. four identifier acceptance filters, each to be applie d to the first eight bits of the identifier. this mode implements four independent filters for the first eight bits of a can 2.0a/b compliant standard identifier. figure 12-6 shows how the 32-bit filter bank (cidar0?cidar3 and cidmr0?cidmr3) produces filter 0 to 3 hits. 4. closed filter. no can message will be copied into the foreground buffer rxfg, and the rxf flag will never be set. figure 12-4. single 32-bit maskable identifier acceptance filter figure 12-5. dual 16-bit maskable acceptance filters id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 cidar0 am7 am0 cidmr0 ac7 ac0 cidar1 am7 am0 cidmr1 ac7 ac0 cidar2 am7 am0 cidmr2 ac7 ac0 cidar3 am7 am0 cidmr3 id accepted (filter 0 hit) id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 cidar0 am7 am0 cidmr0 ac7 ac0 cidar1 am7 am0 cidmr1 id accepted (filter 0 hit) ac7 ac0 cidar2 am7 am0 cidmr2 ac7 ac0 cidar3 am7 am0 cidmr3 id accepted (filter 1 hit) mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 142 freescale semiconductor figure 12-6. quadruple 8-bit maskable acceptance filters ac7 ac0 cidar3 am7 am0 cidmr3 id accepted (filter 3 hit) ac7 ac0 cidar2 am7 am0 cidmr2 id accepted (filter 2 hit) ac7 ac0 cidar1 am7 am0 cidmr1 id accepted (filter 1 hit) id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 cidar0 am7 am0 cidmr0 id accepted (filter 0 hit) interrupts mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 143 12.6 interrupts the mscan08 supports four interrupt vectors mapped on to eleven different interrupt sources, any of which can be individually masked. for details, see 12.13.5 mscan08 receiver flag register (crflg) through 12.13.8 mscan08 transmitter control register . 1. transmit interrupt : at least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for tr ansmission. the txe flags of the empty message buffers are set. 2. receive interrupt : a message has been received successfully and loaded into the foreground receive buffer. this interrupt will be emitted im mediately after receiving the eof symbol. the rxf flag is set. 3. wakeup interrupt : an activity on the can bus occurred during mscan08 internal sleep mode or power-down mode (provid ed slpak = wupie = 1). 4. error interrupt : an overrun, error, or warning conditi on occurred. the receiver flag register (crflg) will indicate one of the following conditions: ? overrun: an overrun condition as described in 12.4.2 receive structures , has occurred. ? receiver warning : the receive error counter has reached the cpu warning limit of 96. ? transmitter warning : the transmit error counter has reached the cpu warning limit of 96. ? receiver error passive : the receive error counter has exceeded the error passive limit of 127 and mscan08 has gone to error passive state. ? transmitter error passive : the transmit error counter has exceeded the error passive limit of 127 and mscan08 has gone to error passive state. ? bus off : the transmit error counter has exceeded 255 and mscan08 has gone to bus off state. 12.6.1 interrupt acknowledge interrupts are directly associated with one or more status flags in either the mscan08 receiver flag register (crflg) or the mscan08 transmitter flag register (ctflg). interrupts are pending as long as one of the corresponding flags is set. the flags in the above registers must be reset within the interrupt handler in order to handshake the interrupt. the flags are reset through writing a ?1? to the corresponding bit position. a flag cannot be cleared if the respective condi tion still prevails. note bit manipulation instructions (bset) shall not be used to clear interrupt flags. 12.6.2 interrupt vectors the mscan08 supports four interrupt vectors as shown in table 12-1 . the vector addresses and the relative interrupt priority are dependent on the chip integration and to be defined. mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 144 freescale semiconductor 12.7 protocol violation protection the mscan08 will protect the user from accidenta lly violating the can prot ocol through programming errors. the protection logic implements the following features: ? the receive and transmit error counters ca nnot be written or otherwise manipulated. ? all registers which control the configuratio n of the mscan08 can not be modified while the mscan08 is on-line. the sftres bit in t he mscan08 module control register (see 12.13.1 mscan08 module control register 0 ) serves as a lock to protect the following registers: ? mscan08 module control register 1 (cmcr1) ? mscan08 bus timing register 0 and 1 (cbtr0 and cbtr1) ? mscan08 identifier acceptance control register (cidac) ? mscan08 identifier acceptance registers (cidar0?3) ? mscan08 identifier mask registers (cidmr0?3) ?the can tx pin is forced to recessive when the ms can08 is in any of the low-power modes. 12.8 low-power modes in addition to normal mode, the mscan08 has three modes with reduced power consumption: sleep, soft reset, and power down. in sleep and soft reset mode , power consumption is reduced by stopping all clocks except those to access the registers. in power-down mode, all clocks are stopped and no power is consumed. the wait and stop instructions put the m cu in low-power consumption stand-by modes. table 12-2 summarizes the combinations of mscan08 and cp u modes. a particular comb ination of modes is entered for the given settings of the bits slpak and sftres. for all modes, an mscan08 wakeup interrupt can occur only if slpak = wupie = 1. table 12-1. mscan08 interrupt vector addresses function source local mask global mask wakeup wupif wupie i bit error interrupts rwrnif rwrnie twrnif twrnie rerrif rerrie terrif terrie boffif boffie ovrif ovrie receive rxf rxfie transmit txe0 txeie0 txe1 txeie1 txe2 txeie2 low-power modes mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 145 . 12.8.1 mscan08 sleep mode the cpu can request the mscan08 to enter the lo w-power mode by asserting the slprq bit in the module configuration register (see figure 12-7 ). the time when the mscan08 enters sleep mode depends on its activity: ? if it is transmitting, it continues to transmit until there is no more message to be transmitted, and then goes into sleep mode ? if it is receiving, it waits for the end of this message and then goes into sleep mode ? if it is neither transmitting or receiv ing, it will immediately go into sleep mode note the application software must avoid setting up a transmission (by clearing or more txe flags) and immediately request sleep mode (by setting slprq). it then depends on the exact sequence of operations whether mscan08 starts transmitting or goes into sleep mode directly. figure 12-7. sleep request/acknowledge cycle table 12-2. mscan08 versus cpu operating modes mscan08 mode cpu mode stop wait or run power down slpak = x (1) sftres = x 1. ?x? means don?t care. sleep slpak = 1 sftres = 0 soft reset slpak = 0 sftres = 1 normal slpak = 0 sftres = 0 mscan08 running slprq = 0 slpak = 0 mcu mscan08 mcu or mscan08 mscan08 sleeping slprq = 1 slpak = 1 sleep request slprq = 1 slpak = 0 mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 146 freescale semiconductor during sleep mode, the slpak flag is set. the a pplication software should use slpak as a handshake indication for the request (slprq) to go into sleep mode. when in sleep mode, the mscan08 stops its internal clocks. however, clocks to allow register ac cesses still run. if the mscan08 is in bus-off state, it stops counting the 128*11 consecutive recessiv e bits due to the stopped clocks. the can tx pin stays in recessive state. if rxf = 1, the message can be read and rxf can be cleared. copying of rxgb into rxfg doesn?t take place while in sleep mode. it is poss ible to access the transmit buffers and to clear the txe flags. no message abort takes place while in sleep mode. the mscan08 leaves sleep mode (wakes-up) when: ? bus activity occurs, or ? the mcu clears the slprq bit, or ? the mcu sets the sftres bit note the mcu cannot clear the slprq bit before the mscan08 is in sleep mode (slpak=1). after wakeup, the mscan08 waits for 11 consecutive re cessive bits to synchronize to the bus. as a consequence, if the mscan08 is woken-up by a can frame, this frame is not received. the receive message buffers (rxfg and rxbg) contain messages if they were received before sleep mode was entered. all pending actions are executed upon wake up: copying of rxbg into rxfg, message aborts and message transmissions. if the mscan08 is still in bus-off state after sleep mode was left, it continues counting the 128*11 consec utive recessive bits. 12.8.2 mscan08 soft reset mode in soft reset mode, the mscan08 is stopped. regist ers can still be accessed. this mode is used to initialize the module configuration, bit timing and the can message filter. see 12.13.1 mscan08 module control register 0 for a complete description of the soft reset mode. when setting the sftres bit, the mscan08 imm ediately stops all ongoing transmissions and receptions, potentially causi ng can protocol violations. note the user is responsible to take care that the mscan08 is not active when soft reset mode is entered. the recommended procedure is to bring the mscan08 into sleep mode before the sftres bit is set. 12.8.3 mscan08 power-down mode the mscan08 is in power-down mode when the cpu is in stop mode. when entering the power-down mode, the mscan08 im mediately stops all ongoing transmissions and receptions, potentially causi ng can protocol violations. note the user is responsible to take care that the mscan08 is not active when power-down mode is entered. the recommended procedure is to bring the mscan08 into sleep mode before the stop instruction is executed. to protect the can bus system from fatal consequences resulting from violations of the above rule, the mscan08 drives the can tx pin into recessive state. in power-down mode, no registers can be accessed. timer link mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 147 mscan08 bus activity can wake the mcu from cp u stop/mscan08 power-down mode. however, until the oscillator starts up and synchronization is achi eved the mscan08 will not respond to incoming data. 12.8.4 cpu wait mode the mscan08 module remains active during cpu wait mode. the mscan08 will stay synchronized to the can bus and generates transmit, receive, and error interrupts to the cpu, if enabled. any such interrupt will bring the mcu out of wait mode. 12.8.5 programmable wakeup function the mscan08 can be programmed to apply a low-pass filter function to the can rx input line while in internal sleep mode (see information on control bit wupm in 12.13.2 mscan08 module control register 1 ). this feature can be used to protect the mscan 08 from wakeup due to short glitches on the can bus lines. such glitches can result from electr omagnetic inference within noisy environments. 12.9 timer link the mscan08 will generate a timer signal whenever a valid frame has been received. because the can specification defines a frame to be valid if no erro rs occurred before the eof field has been transmitted successfully, the timer signal will be generated right after the eof. a pulse of one bit time is generated. as the mscan08 receiver engine also receives the fram es being sent by itself, a timer signal also will be generated after a successful transmission. the previously described timer signal can be routed into the on-chip timer interface module (tim). this signal is connected to channel 0 of timer interface m odule 1 (tim1) under the control of the timer link enable (tlnken) bit in cmcr0. after timer n has been programmed to capture rising edge events, it can be used under software control to generate 16-bit time stamps which can be stored with the received message. 12.10 clock system figure 12-8 shows the structure of the mscan08 clock generation circuitry and its interaction with the clock generation module (cgm). with this flexible clocking scheme the mscan08 is able to handle can bus rates ranging from 10 kbps up to 1 mbps. the clock source bit (clksrc) in the mscan08 module control register (cmcr1) (see 12.13.1 mscan08 module control register 0 ) defines whether the mscan08 is connected to the output of the crystal oscillator or to the pll output. the clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the can protocol are met. note if the system clock is generated from a pll, it is recommended to select the crystal clock source rather than th e system clock source due to jitter considerations, especially at faster can bus rates. mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 148 freescale semiconductor figure 12-8. clocking scheme a programmable prescaler is used to generate out of the mscan08 clock the time quanta (tq) clock. a time quantum is the atomic unit of time handled by the mscan08. a bit time is subdivided into three segments (1) (see figure 12-9 ): ? sync_seg: this segment has a fixed length of one time quantum. signal edges are expected to happen within this section. ? time segment 1: this segm ent includes the prop_seg and the phase_seg1 of the can standard. it can be programmed by setting the para meter tseg1 to consist of 4 to 16 time quanta. ? time segment 2: this segment represent s phase_seg2 of the can standard. it can be programmed by setting the tseg2 parameter to be 2 to 8 time quanta long. the synchronization jump width (sjw) can be programm ed in a range of 1 to 4 time quanta by setting the sjw parameter. 1. for further explanation of the underlying concepts please refer to iso/dis 11 519-1, section 10.3. pll 2 mscan08 prescaler (1 ... 64) osc cgmxclk 2 cgmout (to sim) cgm 2 clksrc mscanclk (2 * bus frequency) bcs f tq = f mscanclk presc value bit rate = no. of time quanta f tq clock system mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 149 the above parameters can be set by programming t he bus timing registers, cbtr0 and cbtr1. see 12.13.3 mscan08 bus timing register 0 and 12.13.4 mscan08 bus timing register 1 . note it is the user?s responsibility to make su re that the bit timing settings are in compliance with the can standard, table 12-8 gives an overview on the can conforming segment settings and the related parameter values. figure 12-9. segments within the bit time . table 12-3. time segment syntax sync_seg system expects transitions to occur on the bus during this period. transmit point a node in transmit mode will transfer a new value to the can bus at this point. sample point a node in receive mode will sample the bus at this point. if the three samples per bit option is selected then this point marks the position of the third sample. table 12-4. can standard compliant bit time segment settings time segment 1 tseg1 time segment 2 tseg2 synchronized jump width sjw 5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1 4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2 5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3 6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3 7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3 8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3 9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3 sync _seg time segment 1 time seg. 2 1 4 ... 16 2 ... 8 8... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + phase_seg1) (phase_seg2) mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 150 freescale semiconductor 12.11 memory map the mscan08 occupies 128 bytes in the cpu0 8 memory space. the absolute mapping is implementation dependent with the base address being a multiple of 128. figure 12-10. mscan08 memory map $0500 control registers 9 bytes $0508 $0509 reserved 5 bytes $050d $050e error counters 2 bytes $050f $0510 identifier filter 8 bytes $0517 $0518 reserved 40 bytes $053f $0540 receive buffer $054f $0550 transmit buffer 0 $055f $0560 transmit buffer 1 $056f $0570 transmit buffer 2 $057f programmer?s model of message storage mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 151 12.12 programmer?s model of message storage this section details the organization of the receive and transmit message buffers and the associated control registers. for reasons of programmer interf ace simplification, the receive and transmit message buffers have the same outline. each message buffer al locates 16 bytes in the memory map containing a 13-byte data structure. an additional transmit buffer pr iority register (tbpr) is defined for the transmit buffers. addr (1) register name $05b0 identifier register 0 $05b1 identifier register 1 $05b2 identifier register 2 $05b3 identifier register 3 $05b4 data segment register 0 $05b5 data segment register 1 $05b6 data segment register 2 $05b7 data segment register 3 $05b8 data segment register 4 $05b9 data segment register 5 $05ba data segment register 6 $05bb data segment register 7 $05bc data length register $05bd transmit buffer priority register (2) $05be unused $05bf unused 1. where b equals the following: b = 4 for receive buffer b = 5 for transmit buffer 0 b = 6 for transmit buffer 1 b = 7 for transmit buffer 2 2. not applicable for receive buffers figure 12-11. message buffer organization mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 152 freescale semiconductor 12.12.1 message buffer outline figure 12-12 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. the mapping of standard identifiers into the idr registers is shown in figure 12-13 . all bits of the 13-byte data structure are undefined out of reset. note the foreground receive buffer can be read anytime but cannot be written. the transmit buffers can be read or written anytime. addr. register bit 7 6 5 4 3 2 1 bit 0 $05b0 idr0 read: id28 id27 id26 id25 id24 id23 id22 id21 write: $05b1 idr1 read: id20 id19 id18 srr (=1) ide (=1) id17 id16 id15 write: $05b2 idr2 read: id14 id13 id12 id11 id10 id9 id8 id7 write: $05b3 idr3 read: id6 id5 id4 id3 id2 id1 id0 rtr write: $05b4 dsr0 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $05b5 dsr1 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $05b6 dsr2 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $05b7 dsr3 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $05b8 dsr4 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $05b9 dsr5 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $05ba dsr6 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $05bb dsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $05bc dlr read: dlc3 dlc2 dlc1 dlc0 write: = unimplemented figure 12-12. receive/transmit message buffer extended identifier (idrn) programmer?s model of message storage mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 153 12.12.2 identifier registers the identifiers consist of either 11 bits (id10?id0) for the standard, or 29 bits (id28?id0) for the extended format. id10/28 is the most significant bit and is transmitted first on the bus during the arbitration procedure. the priority of an identifier is defined to be highest for the smallest binary number. srr ? substitute remote request this fixed recessive bit is used only in extended forma t. it must be set to 1 by the user for transmission buffers and will be stored as received on the can bus for receive buffers. ide ? id extended this flag indicates whether the extended or standard i dentifier format is applied in this buffer. in case of a receive buffer, the flag is set as being received and indicates to the cpu how to process the buffer identifier registers. in case of a transmit buffer, the flag indicates to the mscan08 what type of identifier to send. 1 = extended format, 29 bits 0 = standard format, 11 bits rtr ? remote transmission request this flag reflects the status of the remote transmission request bit in the can frame. in case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. in case of a transmit buffer, this flag defines the setting of the rtr bit to be sent. 1 = remote frame 0 = data frame addr. register bit 7 6 5 4 3 2 1 bit 0 $05b0 idr0 read: id10 id9 id8 id7 id6 id5 id4 id3 write: $05b1 idr1 read: id2 id1 id0 rtr ide (=0) write: $05b2 idr2 read: write: $05b3 idr3 read: write: = unimplemented figure 12-13. standard identifier mapping mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 154 freescale semiconductor 12.12.3 data length register (dlr) this register keeps the data length field of the can frame. dlc3?dlc0 ? data length code bits the data length code contains the number of bytes (data byte count) of the respective message. at transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted bytes is always 0. the data byte count ranges from 0 to 8 for a data frame. table 12-5 shows the effect of setting the dlc bits. 12.12.4 data segment registers (dsrn) the eight data segment registers contain the data to be transmitted or received. the number of bytes to be transmitted or being received is determined by the data length code in the corresponding dlr. 12.12.5 transmit buffer priority registers prio7?prio0 ? local priority this field defines the local priority of the associ ated message buffer. the local priority is used for the internal prioritization process of the mscan08 an d is defined to be highest for the smallest binary number. the mscan08 implements the follow ing internal prioritization mechanism: ? all transmission buffers with a cl eared txe flag participate in the prioritization right before the sof is sent. ? the transmission buffer with the lowest loca l priority field wins the prioritization. ? in case more than one buffer has the same lowest priority, the message buffer with the lower index number wins. table 12-5. data length codes data length code data byte count dlc3 dlc2 dlc1 dlc0 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 address: $05bd bit 7654321bit 0 read: prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 write: reset: unaffected by reset figure 12-14. transmit buffer priority register (tbpr) programmer?s model of control registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 155 12.13 programmer?s mode l of control registers the programmer?s model has been laid out for maximum simplicity and efficiency. figure 12-15 gives an overview on the control register block of the mscan08. addr.register bit 7654321bit 0 $0500 cmcr0 read: 0 0 0 synch tlnken slpak slprq sftres write: $0501 cmcr1 read: 0 0 0 0 0 loopb wupm clksrc write: $0502 cbtr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0503 cbtr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0504 crflg read: wupif rwrnif twrnif rerrif terrif boffif ovrif rxf write: $0505 crier read: wupie rwrnie twrnie rerrie terrie boffie ovrie rxfie write: $0506 ctflg read: 0 abtak2 abtak1 abtak0 0 txe2 txe1 txe0 write: $0507 ctcr read: 0 abtrq2 abtrq1 abtrq0 0 txeie2 txeie1 txeie0 write: $0508 cidac read: 0 idam2 idam1 idam0 0 idhit2 idhit1 idhit0 write: $0509 reserved read: rrrrrrrr write: $050e crxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $050f ctxerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0510 cidar0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0511 cidar1 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0512 cidar2 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0513 cidar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: = unimplemented r = reserved figure 12-15. mscan08 control register structure mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 156 freescale semiconductor 12.13.1 mscan08 module control register 0 synch ? synchronized status this bit indicates whether the mscan08 is synchroni zed to the can bus and as such can participate in the communication process. 1 = mscan08 synchronized to the can bus 0 = mscan08 not synchronized to the can bus tlnken ? timer enable this flag is used to establish a link bet ween the mscan08 and the on-chip timer (see 12.9 timer link ). 1 = the mscan08 timer signal output is connected to the timer input. 0 = the port is connected to the timer input. slpak ? sleep mode acknowledge this flag indicates whether the mscan08 is in module internal sleep mode. it shall be used as a handshake for the sleep mode request (see 12.8.1 mscan08 sleep mode ). if the mscan08 detects bus activity while in sleep mode, it clears the flag. 1 = sleep ? mscan08 in internal sleep mode 0 = wakeup ? mscan08 is not in sleep mode slprq ? sleep request, go to internal sleep mode this flag requests the mscan08 to go into an internal power-saving mode (see 12.8.1 mscan08 sleep mode ). 1 = sleep ? the mscan08 will go into internal sleep mode. 0 = wakeup ? the mscan08 will function normally. $0514 cidmr0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0515 cidmr1 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0516 cidmr2 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0517 cidmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: address: $0500 bit 7654321bit 0 read: 0 0 0 synch tlnken slpak slprq sftres write: reset:00000001 = unimplemented figure 12-16. module control register 0 (cmcr0) addr.register bit 7654321bit 0 = unimplemented r = reserved figure 12-15. mscan08 control register structure (continued) programmer?s model of control registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 157 sftres ? soft reset when this bit is set by the cpu, the mscan08 immediately enters the soft reset state. any ongoing transmission or reception is aborted and synchronization to the bus is lost. the following registers enter and stay in their hard reset state: cmcr0, crflg, crier, ctflg, and ctcr. the registers cmcr1, cbtr0, cbtr1, cidac, cidar0?cidar3, and ci dmr0?cidmr3 can only be written by the cpu when the mscan08 is in soft reset state. the values of the error counters are not affected by soft reset. when this bit is cleared by the cpu, the mscan08 tries to synchronize to the can bus. if the mscan08 is not in bus-off state, it will be synchr onized after 11 recessive bits on the bus; if the mscan08 is in bus-off state, it continues to wait for 128 occurrences of 11 recessive bits. clearing sftres and writing to other bits in cmcr0 must be in separate instructions. 1 = mscan08 in soft reset state 0 = normal operation 12.13.2 mscan08 module control register 1 loopb ? loop back self-test mode when this bit is set, the mscan08 performs an in ternal loop back which can be used for self-test operation: the bit stream output of the transmitter is fed back to the rece iver internally. the can rx input pin is ignored and the can tx output goes to the recessive state (1). the mscan08 behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. in this state the mscan08 ignores the bit sent during the ack slot of the can frame acknowledge field to insure proper recepti on of its own message. both transmit and receive interrupts are generated. 1 = activate loop back self-test mode 0 = normal operation wupm ? wakeup mode this flag defines whether the integrated low-pass filter is applied to protect the mscan08 from spurious wakeups (see 12.8.5 programmable wakeup function ). 1 = mscan08 will wakeup the cpu only in cases of a dominant pulse on the bus which has a length of at least t wup . 0 = mscan08 will wakeup the cpu after any recessive-to-dominant edge on the can bus. address: $0501 bit 7654321bit 0 read:00000 loopb wupm clksrc write: reset:00000000 = unimplemented figure 12-17. module control register (cmcr1) mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 158 freescale semiconductor clksrc ? clock source this flag defines which clock source t he mscan08 module is driven from (see 12.10 clock system ). 1 = the mscan08 clock source is cgmout (see figure 12-8 ). 0 = the mscan08 clock source is cgmxclk/2 (see figure 12-8 ). note the cmcr1 register can be written only if the sftres bit in the mscan08 module control register is set 12.13.3 mscan08 bus timing register 0 sjw1 and sjw0 ? synchronization jump width the synchronization jump width (sjw) defi nes the maximum number of time quanta (t q ) clock cycles by which a bit may be shortened, or lengthened, to achieve resynchronizatio n on data transitions on the bus (see table 12-6 ). brp5?brp0 ? baud rate prescaler these bits determine the time quanta (t q ) clock, which is used to build up the individual bit timing, according to table 12-7 . address: $0502 bit 7654321bit 0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: reset:00000000 figure 12-18. bus timing register 0 (cbtr0) table 12-6. synchronization jump width sjw1 sjw0 synchronization jump width 00 1 t q cycle 01 2 t q cycle 10 3 t q cycle 11 4 t q cycle table 12-7. baud rate prescaler brp5 brp4 brp3 brp2 brp1 brp0 prescaler value (p) 000000 1 000001 2 000010 3 000011 4 :::::: : :::::: : 111111 64 programmer?s model of control registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 159 note the cbtr0 register can be written onl y if the sftres bit in the mscan08 module control register is set. 12.13.4 mscan08 bus timing register 1 samp ? sampling this bit determines the number of serial bus samples to be taken per bit time. if set, three samples per bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. for higher bit rates, samp should be cleared, which m eans that only one sample will be taken per bit. 1 = three samples per bit (1) 0 = one sample per bit tseg22?tseg10 ? time segment time segments within the bit time fix the number of clock cycles per bit time and the location of the sample point. time segment 1 (tseg1) and time segment 2 (tseg2) are programmable as shown in table 12-8 . the bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (t q ) clock cycles per bit as shown in table 12-4 ). note the cbtr1 register can only be writt en if the sftres bit in the mscan08 module control register is set. address: $0503 bit 7654321bit 0 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: reset:00000000 figure 12-19. bus timing register 1 (cbtr1) 1. in this case phase_seg1 mu st be at least 2 time quanta. table 12-8. time segment values tseg13 tseg12 tseg11 tseg10 time segment 1 tseg22 tseg21 tseg20 time segment 2 0000 1 t q cycle (1) 1. this setting is not valid. please refer to table 12-4 for valid settings. 000 1 t q cycle (1) 0001 2 t q cycles (1) 001 2 t q cycles 0010 3t q cycles (1) ... . 0011 4 t q cycles ... . .... . 111 8t q cycles .... . 1111 16 t q cycles bit time = pres value f mscanclk ? number of time quanta mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 160 freescale semiconductor 12.13.5 mscan08 r eceiver flag register (crflg) all bits of this register are read and clear only. a flag can be cleared by writing a 1 to the corresponding bit position. a flag can be cleared only when the condition which caus ed the setting is valid no more. writing a 0 has no effect on the flag setting. every flag has an associated interrupt enable flag in the crier register. a hard or soft reset will clear the register. wupif ? wakeup interrupt flag if the mscan08 detects bus activity while in sleep mode, it sets the wupif flag. if not masked, a wakeup interrupt is pending while this flag is set. 1 = mscan08 has detected activity on the bus and requested wakeup. 0 = no wakeup interrupt has occurred. rwrnif ? receiver warning interrupt flag this flag is set when the mscan08 goes into warning status due to the receive error counter (rec) exceeding 96 and neither one of the error interrupt flags or the bus-off interrupt flag is set (1) . if not masked, an error interrupt is pending while this flag is set. 1 = mscan08 has gone into receiver warning status. 0 = no receiver warning status has been reached. twrnif ? transmitter warning interrupt flag this flag is set when the mscan08 goes into warn ing status due to the transmit error counter (tec) exceeding 96 and neither one of the error interrupt flags or the bus-off interrupt flag is set (2) . if not masked, an error interrupt is pending while this flag is set. 1 = mscan08 has gone into transmitter warning status. 0 = no transmitter warning status has been reached. rerrif ? receiver error passive interrupt flag this flag is set when the mscan08 goes into error passive status due to the receive error counter exceeding 127 and the bus-off interrupt flag is not set (3) . if not masked, an error interrupt is pending while this flag is set. 1 = mscan08 has gone into receiver error passive status. 0 = no receiver error passive status has been reached. address: $0504 bit 7654321bit 0 read: wupif rwrnif twrnif rerrif terrif boffif ovrif rxf write: reset:00000000 figure 12-20. receiver flag register (crflg) 1. condition to set the flag: rwrnif = (96 rec) & rerrif & terrif & boffif 2. condition to set the flag: twrnif = (96 tec) & rerrif & terrif & boffif 3. condition to set the flag: rerrif = (127 rec 255) & boffif programmer?s model of control registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 161 terrif ? transmitter error passive interrupt flag this flag is set when the mscan08 goes into error passive status due to the transmit error counter exceeding 127 and the bus-off interrupt flag is not set (1) . if not masked, an error interrupt is pending while this flag is set. 1 = mscan08 went into transmit error passive status. 0 = no transmit error passive status has been reached. boffif ? bus-off interrupt flag this flag is set when the mscan08 goes into bu s-off status, due to the transmit error counter exceeding 255. it cannot be cleared before the mscan08 has monitored 128 times 11 consecutive ?recessive? bits on the bus. if not masked, an error interrupt is pending while this flag is set. 1 = mscan08has gone into bus-off status. 0 = no bus-off status has been reached. ovrif ? overrun interrupt flag this flag is set when a data overrun condition occurs . if not masked, an error interrupt is pending while this flag is set. 1 = a data overrun has been detected since last clearing the flag. 0 = no data overrun has occurred. rxf ? receive buffer full the rxf flag is set by the mscan08 when a new me ssage is available in the foreground receive buffer. this flag indicates whether the buffer is loaded with a correctly received message. after the cpu has read that message from the receive buffer the rxf flag must be cleared to release the buffer. a set rxf flag prohibits the exchange of the background receive buffer into the foreground buffer. if not masked, a receive interrupt is pending while this flag is set. 1 = the receive buffer is full. a new message is available. 0 = the receive buffer is released (not full). note to ensure data integrity, no registers of the receive buffer shall be read while the rxf flag is cleared. the crflg register is held in the reset state when the sftres bit in cmcr0 is set. 1. condition to set the flag: terrif = (128 tec 255) & boffif mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 162 freescale semiconductor 12.13.6 mscan08 receiver inte rrupt enable register wupie ? wakeup interrupt enable 1 = a wakeup event will result in a wakeup interrupt. 0 = no interrupt will be generated from this event. rwrnie ? receiver warning interrupt enable 1 = a receiver warning status event will result in an error interrupt. 0 = no interrupt is generated from this event. twrnie ? transmitter warning interrupt enable 1 = a transmitter warning status event will result in an error interrupt. 0 = no interrupt is generated from this event. rerrie ? receiver error passive interrupt enable 1 = a receiver error passive status event will result in an error interrupt. 0 = no interrupt is generated from this event. terrie ? transmitter error passive interrupt enable 1 = a transmitter error passive status event will result in an error interrupt. 0 = no interrupt is generated from this event. boffie ? bus-off interrupt enable 1 = a bus-off event will result in an error interrupt. 0 = no interrupt is generated from this event. ovrie ? overrun interrupt enable 1 = an overrun event will result in an error interrupt. 0 = no interrupt is generated from this event. rxfie ? receiver full interrupt enable 1 = a receive buffer full (successful message reception) event will result in a receive interrupt. 0 = no interrupt will be generated from this event. note the crier register is held in the reset state when the sftres bit in cmcr0 is set. address: $0505 bit 7654321bit 0 read: wupie rwrnie twrnie rerrie terrie boffie ovrie rxfie write: reset:00000000 figure 12-21. receiver interrupt enable register (crier) programmer?s model of control registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 163 12.13.7 mscan08 transm itter flag register the abort acknowledge flags are read only. the tran smitter buffer empty flags are read and clear only. a flag can be cleared by writing a 1 to the corresponding bit position. writing a 0 has no effect on the flag setting. the transmitter buffer empty flags each have an associated interrupt enable bit in the ctcr register. a hard or soft reset will resets the register. abtak2?abtak0 ? abort acknowledge this flag acknowledges that a message has been aborted due to a pending abort request from the cpu. after a particular message buffer has been flagged empty, this flag can be used by the application software to identify whether the messag e has been aborted successfully or has been sent. the abtakx flag is cleared implicitly whenev er the corresponding txe flag is cleared. 1 = the message has been aborted. 0 = the message has not been aborted, thus has been sent out. txe2?txe0 ? transmitter empty this flag indicates that the associated transmit message buffer is empty, thus not scheduled for transmission. the cpu must handshake (clear) the flag after a message has been set up in the transmit buffer and is due for transmission. the mscan08 sets the flag after the message has been sent successfully. the flag is also set by the mscan08 when the transmission request was successfully aborted due to a pending abort request (see 12.12.5 transmit buffer priority registers ). if not masked, a receive interrupt is pending while this flag is set. clearing a txex flag also clears the correspon ding abtakx flag (abtak, see above). when a txex flag is set, the corresponding abtrq x bit (abtrq) is cleared. see 12.13.8 mscan08 transmitter control register 1 = the associated message buffer is empty (not scheduled). 0 = the associated message buffer is full (loaded with a message due for transmission). note to ensure data integrity, no registers of the transmit buffers should be written to while the associated txe flag is cleared. the ctflg register is held in the reset state when the sftres bit in cmcr0 is set. address: $0506 5 bit 7654321bit 0 read: 0 abtak2 abtak1 abtak0 0 txe2 txe1 txe0 write: reset:00000111 = unimplemented figure 12-22. transmitter flag register (ctflg) mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 164 freescale semiconductor 12.13.8 mscan08 transmitter control register abtrq2?abtrq0 ? abort request the cpu sets an abtrqx bit to request that an already scheduled message buffer (txe = 0) be aborted. the mscan08 will grant the request if th e message has not already started transmission, or if the transmission is not successful (lost ar bitration or error). when a message is aborted the associated txe and the abort acknowledge flag (abtak) (see 12.13.7 mscan08 transmitter flag register ) will be set and an txe interrupt is generated if enabled. the cpu cannot reset abtrqx. abtrqx is cleared implicitly whenever the associated txe flag is set. 1 = abort request pending 0 = no abort request note the software must not clear one or more of the txe flags in ctflg and simultaneously set the respective abtrq bit(s). txeie2?txeie0 ? transmitter empty interrupt enable 1 = a transmitter empty (transmit buffer available for transmission) event results in a transmitter empty interrupt. 0 = no interrupt is generated from this event. note the ctcr register is held in the reset state when the sftres bit in cmcr0 is set. 12.13.9 mscan08 identifier acceptance control register address: $0507 bit 7654321bit 0 read: 0 abtrq2 abtrq1 abtrq0 0 txeie2 txeie1 txeie0 write: reset:00000000 = unimplemented figure 12-23. transmitter control register (ctcr) address: $0508 bit 7654321bit 0 read: 0 idam2 idam1 idam0 0 idhit2 idhit1 idhit0 write: reset:00000000 = unimplemented figure 12-24. identifier accepta nce control register (cidac) programmer?s model of control registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 165 idam2?idam0? identifier acceptance mode the cpu sets these flags to define the i dentifier acceptance filter organization (see 12.5 identifier acceptance filter ). table 12-9 summarizes the different settings. in ?filter closed? mode no messages will be accepted so that the foreground buffer will never be reloaded. idhit2?idhit0? identifier acceptance hit indicator the mscan08 sets these flags to indicate an identifier acceptance hit (see 12.5 identifier acceptance filter ). table 12-9 summarizes the different settings. the idhit indicators are always related to the message in the foreground buffer. when a message gets copied from the background to the foregrou nd buffer, the indicators are updated as well. note the cidac register can be written only if the sftres bit in the cmcr0 is set. 12.13.10 mscan08 recei ve error counter this read-only register reflects the status of the mscan08 receive error counter. table 12-9. identifier acceptance mode settings idam2 idam1 idam0 identifier acceptance mode 0 0 0 single 32-bit acceptance filter 0 0 1 two 16-bit acceptance filter 0 1 0 four 8-bit acceptance filters 0 1 1 filter closed 1xxreserved table 12-10. identifier acceptance hit indication idhit2 idhit1 idhit0 iden tifier acceptance hit 0 0 0 filter 0 hit 0 0 1 filter 1 hit 0 1 0 filter 2 hit 0 1 1 filter 3 hit 1xxreserved address: $050e bit 7654321bit 0 read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: reset:00000000 = unimplemented figure 12-25. receiver error counter (crxerr) mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 166 freescale semiconductor 12.13.11 mscan08 transm it error counter this read-only register reflects the status of the mscan08 transmit error counter. note both error counters may only be read when in sleep or soft reset mode. 12.13.12 mscan08 identifier a cceptance registers on reception each message is written into the back ground receive buffer. the cpu is only signalled to read the message, however, if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message will be overwritten by the next message (dropped). the acceptance registers of the mscan08 are applied on the idr0 to idr3 registers of incoming messages in a bit by bit manner. for extended identifiers, all four acceptance and mask registers are applied. for standard identifiers only the first two (cidmr0/cidmr1 and cidar0/cidar1) are applied. address: $050f bit 7654321bit 0 read: txerr7 txerr6 txerr5 txer r4 txerr3 txerr2 txerr1 txerr0 write: reset:00000000 = unimplemented figure 12-26. transmit error counter (ctxerr) cidar0 address: $0510 bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset cidar1 address: $050511 bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset cidar2 address: $0512 bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset cidar3 address: $0513 bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset figure 12-27. identifier acceptance registers (cidar0?cidar3) programmer?s model of control registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 167 ac7?ac0 ? acceptance code bits ac7?ac0 comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (idrn) of the receive message buffer are compared. the result of this comparison is then masked with the corresponding identifier mask register. note the cidar0?cidar3 registers can be wr itten only if the sftres bit in cmcr0 is set 12.13.13 mscan08 iden tifier mask regist ers (cidmr0?cidmr3) the identifier mask registers specify which of the co rresponding bits in the identif ier acceptance register are relevant for acceptance filtering. for standard identif iers it is required to program the last three bits (am2?am0) in the mask register cidmr1 to ?don?t care?. am7?am0 ? acceptance mask bits if a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifi er bit before a match will be detected. the message will be accepted if all such bits match. if a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register will not af fect whether or not the message is accepted. 1 = ignore corresponding acceptance code register bit. 0 = match corresponding acceptance code register and identifier bits. note the cidmr0?cidmr3 registers can be written only if the sftres bit in the cmcr0 is set cidmro address: $0514 bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset cidmr1 address: $0515 bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset cidmr2 address: $0516 bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset cidmr3 address: $0517 bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset figure 12-28. identifier mask registers (cidmr0?cidmr3) mscan08 controller (mscan08) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 168 freescale semiconductor mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 169 chapter 13 input/output (i/o) ports 13.1 introduction bidirectional input-output (i/o) pins form seven paralle l ports. all i/o pins are programmable as inputs or outputs. all individual bits within port a, port c, port d and port f are software configurable with pullup devices if configured as input port bits. the pull up devices are automatically and dynamically disabled when a port bit is switched to output mode. 13.2 unused pin termination input pins and i/o port pins that are not used in t he application must be terminated. this prevents excess current caused by floating inputs, and enhances immu nity during noise or transient events. termination methods include: 1. configuring unused pins as outputs and driving high or low; 2. configuring unused pins as i nputs and enabling internal pull-ups; 3. configuring unused pins as inputs and us ing external pull-up or pull-down resistors. never connect unused pins directly to v dd or v ss . since some general-purpose i/o pins are not available on all packages, these pins must be terminated as well. either method 1 or 2 above are appropriate. addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 173. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 176. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 178. read: 1 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) see page 180. read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset = unimplemented figure 13-1. i/o port register summary (sheet 1 of 3) input/output (i/o) ports mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 170 freescale semiconductor $0004 data direction register a (ddra) see page 174. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 176. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) see page 178. read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) see page 181. read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) see page 183. read: 0 0 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $000c data direction register e (ddre) see page 184. read: 0 0 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 $000d port a input pullup enable register (ptapue) see page 175. read: ptapue7 ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000e port c input pullup enable register (ptcpue) see page 180. read: 0 ptcpue6 ptcpue5 ptcpue4 ptcpue3 ptcpue2 ptcpue1 ptcpue0 write: reset:00000000 $000f port d input pullup enable register (ptdpue) see page 182. read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset:00000000 $0440 port f data register (ptf) see page 185. read: ptf7 ptf6 ptf5 ptf4 ptaf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset $0441 port g data register (ptg) see page 186. read: ptg7 ptg6 ptg5 ptg4 ptg3 ptg2 ptg1 ptg0 write: reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented figure 13-1. i/o port register summary (sheet 2 of 3) unused pin termination mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 171 $0444 data direction register f (ddrf) see page 185. read: ddrf7 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset:00000000 $0445 data direction register g (ddrg) see page 187. read: ddrg7 ddrg6 ddrg5 ddrg4 ddrg3 ddrg2 ddrg1 ddrg0 write: reset:00000000 table 13-1. port control register bits summary port bit ddr module control module control pin a 0ddra0 kbd kbie0 adc[15:8] adch4?adch0 pta0/kbd0/ad8 1 ddra1 kbie1 pta1/kbd1/ad9 2 ddra2 kbie2 pta2/kbd2/ad10 3 ddra3 kbie3 pta3/kbd3/ad11 4 ddra4 kbie4 pta4/kbd4/ad12 5 ddra5 kbie5 pta5/kbd5/ad13 6 ddra6 kbie6 pta6/kbd6/ad14 7 ddra7 kbie7 pta7/kbd7/ad15 b 0ddrb0 adc adch4?adch0 ? ? ptb0/ad0 1ddrb1 ptb1/ad1 2ddrb2 ptb2/ad2 3ddrb3 ptb3/ad3 4ddrb4 ptb4/ad4 5ddrb5 ptb5/ad5 6ddrb6 ptb6/ad6 7ddrb7 ptb7/ad7 c 0 ddrc0 mscan canen ?? ptc0 1 ddrc1 ptc1 2 ddrc2 ptc2 3 ddrc3 ptc3 4 ddrc4 ptc4 5 ddrc5 ptc5 6 ddrc6 ptc6 ? continued on next page addr.register name bit 7654321bit 0 = unimplemented figure 13-1. i/o port register summary (sheet 3 of 3) input/output (i/o) ports mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 172 freescale semiconductor d 0 ddrd0 spi spe ?? ptd0/ss /mclk 1 ddrd1 ptd1/miso 2 ddrd2 ptd2/mosi 3 ddrd3 ptd3/spsck 4 ddrd4 tim1 els0b:els0a ptd4/t1ch0 5 ddrd5 els1b:els1a ptd5/t1ch1 6 ddrd6 tim2 els0b:els0a ptd6/t2ch0 7 ddrd7 els1b:els1a ptd7/t2ch1 e 0ddre0 sci ensci ?? pte0/txd 1ddre1 pte1/rxd 2ddre2 pte2 3ddre3 pte3 4ddre4 pte4 5ddre5 pte5 f 0 ddrf0 ?? ptf0 1 ddrf1 ptf1 2 ddrf2 ptf2 3 ddrf3 ptf3 4 ddrf4 tim2 els2b:els2a ptf4/t2ch2 5 ddrf5 els3b:els3a ptf5/t2ch3 6 ddrf6 els4b:els4a ptf6/t2ch4 7 ddrf7 els5b:els5a ptf7/t2ch5 g 0 ddrg0 adc adch[23:16] ? ? ptg0/ad16 1 ddrg1 ptg1/ad17 2 ddrg2 ptg2/ad18 3 ddrg3 ptg3/ad19 4 ddrg4 ptg4/ad20 5 ddrg5 ptg5/ad21 6 ddrg6 ptg6/ad22 7 ddrg7 ptg7/ad23 table 13-1. port control register bits summary (continued) port bit ddr module control module control pin port a mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 173 13.3 port a port a is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (kbi) module and the adc module. port a also has software configurable pullup devices if configured as an input port. 13.3.1 port a data register the port a data register (pta) contains a data latch for each of the eight port a pins. pta7?pta0 ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction regi ster a. reset has no effect on port a data. kbd7?kbd0 ? keyboard inputs the keyboard interrupt enable bits, kbie7?kbie0, in the keyboard interrupt control register (kbicr) enable the port a pins as external interrupt pins. see chapter 9 keyboard interrupt module (kbi) ad15?ad8 ? analog-to-digital input bits ad15?ad8 are pins used for the input channels to t he analog-to-digital converter module. the channel select bits in the adc status and control register define which port a pin will be used as an adc input and overrides any control from the port i/o logic by forcing that pin as the input to the analog circuitry. note care must be taken when reading port a while applying analog voltages to ad15?ad8 pins. if the appropriate adc channel is not enabled, excessive current drain may occur if analog voltages are applied to the ptax/kbdx/adx pin, while pta is read as a digital input during the cpu read cycle. those ports not sele cted as analog input channels are considered digital i/o ports. address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternate function: kbd7 kbd6 kbd5 kbd4 kbd3 kbd2 kbd1 kbd0 alternate function: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 figure 13-2. port a data register (pta) input/output (i/o) ports mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 174 freescale semiconductor 13.3.2 data dir ection register a data direction register a (ddra) determines whether eac h port a pin is an input or an output. writing a 1 to a ddra bit enables the output buffer for the co rresponding port a pin; a 0 disables the output buffer. ddra7?ddra0 ? data direction register a bits these read/write bits control port a data directio n. reset clears ddra7?ddra0, configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note avoid glitches on port a pins by writin g to the port a data register before changing data direction regist er a bits from 0 to 1. figure 13-4 shows the port a i/o logic. when bit ddrax is a 1, reading address $0000 reads the ptax data latch. when bit ddrax is a 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 13-2 summarizes the operation of the port a pins. figure 13-4. port a i/o circuit address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 13-3. data direction register a (ddra) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus v dd ptapuex internal pullup device port a mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 175 13.3.3 port a input pullup enable register the port a input pullup enable register (ptapue) cont ains a software configur able pullup device for each of the eight port a pins. each bit is individually conf igurable and requires that the data direction register, ddra, bit be configured as an input. ea ch pullup is automati cally and dynamically disabled when a port bit?s ddra is configured for output mode. note pullup or pulldown resistors are automatically selected for keyboard interrupt pins depending on the bit settings in the keyboard interrupt polarity register (intkbipr) see 9.7.3 keyboard interrupt polarity register . ptapue7?ptapue0 ? port a input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port bit. 1 = corresponding port a pin configured to have internal pullup 0 = corresponding port a pin has internal pullup disconnected table 13-2. port a pin functions ptapue bit ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 10 x (1) 1. x = don?t care input, v dd (2) 2. i/o pin pulled up to v dd by internal pullup device ddra7?ddra0 pin pta7?pta0 (3) 3. writing affects data register, but does not affect input. 00x input, hi-z (4) 4. hi-z = high impedance ddra7?ddra0 pin pta7?pta0 (3) x 1 x output ddra7?ddra0 pta7?pta0 pta7?pta0 address: $000d bit 7654321bit 0 read: ptapue7 ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 figure 13-5. port a input pullup enable register (ptapue) input/output (i/o) ports mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 176 freescale semiconductor 13.4 port b port b is an 8-bit special-function port that shares al l eight of its pins with the analog-to-digital converter (adc) module. 13.4.1 port b data register the port b data register (ptb) contains a data latch for each of the eight port pins. ptb7?ptb0 ? port b data bits these read/write bits are software-programmable. data direction of each port b pin is under the control of the corresponding bit in data direction regi ster b. reset has no effect on port b data. ad7?ad0 ? analog-to-digital input bits ad7?ad0 are pins used for the input channels to the analog-to-digital converter module. the channel select bits in the adc status and control register define which port b pin will be used as an adc input and overrides any control from the port i/o logic by forcing that pin as the input to the analog circuitry. note care must be taken when reading port b while applying analog voltages to ad7?ad0 pins. if the appropriate adc channel is not enabled, excessive current drain may occur if analog voltages are applied to the ptbx/adx pin, while ptb is read as a digital input during the cpu read cycle. those ports not selected as analog input channels are considered digital i/o ports. 13.4.2 data dir ection register b data direction register b (ddrb) determines whether eac h port b pin is an input or an output. writing a 1 to a ddrb bit enables the output buffer for the co rresponding port b pin; a 0 disables the output buffer. address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternate function: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 figure 13-6. port b data register (ptb) address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 13-7. data direction register b (ddrb) port b mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 177 ddrb7?ddrb0 ? data direction register b bits these read/write bits control port b data directio n. reset clears ddrb7?ddrb0, configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note avoid glitches on port b pins by writin g to the port b data register before changing data direction regist er b bits from 0 to 1. figure 13-8 shows the port b i/o logic. when bit ddrbx is a 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 13-3 summarizes the operation of the port b pins. figure 13-8. port b i/o circuit table 13-3. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrb7?ddrb0 pin ptb7?ptb0 (3) 3. writing affects data register, but does not affect input. 1 x output ddrb7?ddrb0 ptb7?ptb0 ptb7?ptb0 read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus input/output (i/o) ports mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 178 freescale semiconductor 13.5 port c port c is a 7-bit, general-purpose bidirectional i/o port. port c also has software configurable pullup devices if configured as an input port. ptc[ 1:0] are shared with the mscan module. 13.5.1 port c data register the port c data register (ptc) contains a dat a latch for each of the seven port c pins. note bit 6 through bit 2 of ptc are not available in the 32-pin lqfp package. ptc6?ptc0 ? port c data bits these read/write bits are software-programmable. da ta direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. can rx and can tx ? mscan08 bits the can rx ?can tx pins are the mscan08 modules receive and transmit pins. the canen bit in the mscan08 control register determines, whether the ptc1/can rx ?ptc0/can tx pins are mscan08 pins or general-purpose i/o pins. see chapter 12 mscan08 controller (mscan08). 13.5.2 data dir ection register c data direction register c (ddrc) determines whether eac h port c pin is an input or an output. writing a 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a 0 disables the output buffer. address: $0002 bit 7654321bit 0 read: 1 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset alternate function: can rx can tx = unimplemented figure 13-9. port c data register (ptc) address: $0006 bit 7654321bit 0 read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 = unimplemented figure 13-10. data direction register c (ddrc) port c mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 179 ddrc6?ddrc0 ? data direction register c bits these read/write bits control po rt c data direction. reset clears ddrc6?ddrc0, configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note avoid glitches on port c pins by writin g to the port c data register before changing data direction regist er c bits from 0 to 1. figure 13-11 shows the port c i/o logic. when bit ddrcx is a 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 13-4 summarizes the operation of the port c pins. figure 13-11. port c i/o circuit table 13-4. port c pin functions ptcpue bit ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 10 x (1) 1. x = don?t care input, v dd (2) 2. i/o pin pulled up to v dd by internal pullup device. ddrc6?ddrc0 pin ptc6?ptc0 (3) 3. writing affects data register, but does not affect input. 00x input, hi-z (4) 4. hi-z = high impedance ddrc6?ddrc0 pin ptc6?ptc0 (3) x 1 x output ddrc6?ddrc0 ptc6?ptc0 ptc6?ptc0 read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus v dd ptcpuex internal pullup device input/output (i/o) ports mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 180 freescale semiconductor 13.5.3 port c input pullup enable register the port c input pullup enable register (ptcpue) co ntains a software configur able pullup device for each of the seven port c pins. each bit is individually c onfigurable and requires that the data direction register, ddrc, bit be configured as an input. each pullup is automatically and dynamically disabled when a port bit?s ddrc is configured for output mode. ptcpue6?ptcpue0 ? port c input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port bit. 1 = corresponding port c pin configured to have internal pullup 0 = corresponding port c pin internal pullup disconnected 13.6 port d port d is an 8-bit special-function port that shares four of its pins with the serial peripheral interface (spi) module and four of its pins with two timer interfac e (tim1 and tim2) modules. port d also has software configurable pullup devices if conf igured as an input port. ptd0 is shared with the mclk output. 13.6.1 port d data register the port d data register (ptd) contains a data latch for each of the eight port d pins. ptd7?ptd0 ? port d data bits these read/write bits are software-programmable. da ta direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. t2ch1 and t2ch0 ? timer 2 channel i/o bits the ptd5/t2ch1?ptd4/t2ch0 pins are the tim2 input capture/output compare pins. the edge/level select bits, elsxb:elsxa, dete rmine whether the ptd7/t2ch1?ptd 6/t2ch0 pins are timer channel i/o pins or general-purpose i/o pins. see chapter 18 timer interface module (tim1) and chapter 19 timer interface module (tim2) . address: $000e bit 7654321bit 0 read: 0 ptcpue6 ptcpue5 ptcpue4 ptcpue3 ptcpue2 ptcpue1 ptcpue0 write: reset:00000000 = unimplemented figure 13-12. port c input pullup enable register (ptcpue) address: $0003 bit 7654321bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset alternate function: t2ch1 t2ch0 t1ch1 t1ch0 spsck mosi miso ss mclk figure 13-13. port d data register (ptd) port d mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 181 t1ch1 and t1ch0 ? timer 1 channel i/o bits the ptd7/t1ch1?ptd6/t1ch0 pins are the tim1 input capture/output compare pins. the edge/level select bits, elsxb and elsxa, determine whether the ptd7/t1ch1?ptd6/t1ch0 pins are timer channel i/o pins or general-purpose i/o pins. see chapter 18 timer interface module (tim1) and chapter 19 timer interface module (tim2) . spsck ? spi serial clock the ptd3/spsck pin is the serial clock input of the spi module. when the spe bit is clear, the ptd3/spsck pin is availabl e for general-purpose i/o. mosi ? master out/slave in the ptd2/mosi pin is the master out/slave in term inal of the spi module. when the spe bit is clear, the ptd2/mosi pin is available for general-purpose i/o. miso ? master in/slave out the ptd1/miso pin is the master in/slave out term inal of the spi module. when the spi enable bit, spe, is clear, the spi module is di sabled, and the ptd1/miso pin is available for general-purpose i/o. ss ? slave select the ptd0/ss pin is the slave select input of the sp i module. when the spe bit is clear, or when the spi master bit, spmstr, is set, the ptd0/ss pin is available for gener al-purpose i/o. when the spi is enabled, the ddrd0 bit in data direction register d (ddrd) has no effect on the ptd0/ss pin. data direction register d (ddrd) does not affect the data direction of port d pins that are being used by the spi module. however, the ddrd bits always determine whether r eading port d returns the states of the latches or the states of the pins. see table 13-5 . 13.6.2 data dir ection register d data direction register d (ddrd) determines whether eac h port d pin is an input or an output. writing a 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a 0 disables the output buffer. ddrd7?ddrd0 ? data direction register d bits these read/write bits control po rt d data direction. reset clears ddrd7?ddrd0, configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note avoid glitches on port d pins by writin g to the port d data register before changing data direction regist er d bits from 0 to 1. figure 13-15 shows the port d i/o logic. address: $0007 bit 7654321bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 13-14. data direction register d (ddrd) input/output (i/o) ports mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 182 freescale semiconductor when bit ddrdx is a 1, reading address $0003 reads the ptdx data latch. when bit ddrdx is a 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 13-5 summarizes the operation of the port d pins. figure 13-15. port d i/o circuit 13.6.3 port d input pullup enable register the port d input pullup enable register (ptdpue) co ntains a software configur able pullup device for each of the eight port d pins. each bit is individually configurable and require s that the data direction register, ddrd, bit be configured as an input. each pullup is automatically and dynamically disabled when a port bit?s ddrd is configured for output mode. table 13-5. port d pin functions ptdpue bit ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 10 x (1) 1. x = don?t care input, v dd (2) 2. i/o pin pulled up to v dd by internal pullup device. ddrd7?ddrd0 pin ptd7?ptd0 (3) 3. writing affects data register, but does not affect input. 00x input, hi-z (4) 4. hi-z = high imp[edance ddrd7?ddrd0 pin ptd7?ptd0 (3) x 1 x output ddrd7?ddrd0 ptd7?ptd0 ptd7?ptd0 address: $000f bit 7654321bit 0 read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset:00000000 figure 13-16. port d input pullup enable register (ptdpue) read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus v dd ptdpuex internal pullup device port e mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 183 ptdpue7?ptdpue0 ? port d input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port bit. 1 = corresponding port d pin configured to have internal pullup 0 = corresponding port d pin ha s internal pullup disconnected 13.7 port e port e is a 6-bit special-function port that shares tw o of its pins with the enhanced serial communications interface (esci) module. 13.7.1 port e data register the port e data register contains a data latch for each of the six port e pins. pte5?pte0 ? port e data bits these read/write bits are software-programmable. data direction of each port e pin is under the control of the corresponding bit in data direction regi ster e. reset has no effect on port e data. note data direction register e (ddre) does not affect the data direction of port e pins that are being used by the esci module. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. see table 13-6 . rxd ? sci receive data input the pte1/rxd pin is the receive data input for the esci module. when the enable sci bit, ensci, is clear, the esci module is disabled, and the pte1/rxd pin is available for general-purpose i/o. see chapter 14 enhanced serial commun ications interface (esci) module . txd ? sci transmit data output the pte0/txd pin is the transmit data output for the esci module. when the enable sci bit, ensci, is clear, the esci module is disabled, and the pte0/t xd pin is available for general-purpose i/o. see chapter 14 enhanced serial communi cations interface (esci) module . address: $0008 bit 7654321bit 0 read: 0 0 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset alternate function: rxd txd = unimplemented figure 13-17. port e data register (pte) input/output (i/o) ports mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 184 freescale semiconductor 13.7.2 data dir ection register e data direction register e (ddre) determines whether eac h port e pin is an input or an output. writing a 1 to a ddre bit enables the output buffer for the co rresponding port e pin; a 0 disables the output buffer. ddre5?ddre0 ? data direction register e bits these read/write bits control port e data directio n. reset clears ddre5?ddre0, configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note avoid glitches on port e pins by writin g to the port e data register before changing data direction regist er e bits from 0 to 1. figure 13-19 shows the port e i/o logic. when bit ddrex is a 1, reading address $0008 reads the ptex data latch. when bit ddrex is a 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 13-6 summarizes the operation of the port e pins. figure 13-19. port e i/o circuit address: $000c bit 7654321bit 0 read: 0 0 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 = unimplemented figure 13-18. data direction register e (ddre) table 13-6. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddre5?ddre0 pin pte5?pte0 (3) 3. writing affects data register, but does not affect input. 1 x output ddre5?ddre0 pte5?pte0 pte5?pte0 read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus port f mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 185 13.8 port f port f is an 8-bit special-function port that shares four of its pins with the timer interface (tim2) module. 13.8.1 port f data register the port f data register (ptf) contains a data latch for each of the eight port f pins. ptf7?ptf0 ? port f data bits these read/write bits are software-programmable. data direction of each port f pin is under the control of the corresponding bit in data direction re gister f. reset has no effect on port f data. t2ch5?t2ch2 ? timer 2 channel i/o bits the ptf7/t2ch5?ptf4/t2ch2 pins are the tim2 i nput capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the ptf7/t2ch5?ptf4/t2ch2 pins are timer channel i/o pins or general-purpose i/o pins. see chapter 18 timer interface module (tim1) and chapter 19 timer interface module (tim2) . 13.8.2 data dir ection register f data direction register f (ddrf) determines whether eac h port f pin is an input or an output. writing a 1 to a ddrf bit enables the output buffer for the corresponding port f pin; a 0 disables the output buffer. ddrf7?ddrf0 ? data direction register f bits these read/write bits control port f data directi on. reset clears ddrf7?ddrf0, configuring all port f pins as inputs. 1 = corresponding port f pin configured as output 0 = corresponding port f pin configured as input note avoid glitches on port f pins by writ ing to the port f data register before changing data direction regist er f bits from 0 to 1. figure 13-22 shows the port f i/o logic. address: $0440 bit 7654321bit 0 read: ptf7 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset alternate function: t2ch5 t2ch4 t2ch3 t2ch2 = unimplemented figure 13-20. port f data register (ptf) address: $0444 bit 7654321bit 0 read: ddrf7 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset:00000000 figure 13-21. data direction register f (ddrf) input/output (i/o) ports mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 186 freescale semiconductor figure 13-22. port f i/o circuit when bit ddrfx is a 1, reading address $0440 reads the ptfx data latch. when bit ddrfx is a 0, reading address $0440 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 13-7 summarizes the operation of the port f pins. 13.9 port g port g is an 8-bit special-function port that shares all eight of its pins with the analog-to-digital converter (adc) module. 13.9.1 port g data register the port g data register (ptg) contains a data latch for each of the eight port pins. table 13-7. port f pin functions ddrf bit ptf bit i/o pin mode accesses to ddrf accesses to ptf read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrf7?ddrf0 pin ptf7?ptf0 (3) 3. writing affects data register, but does not affect input. 1 x output ddrf7?ddrf0 ptf7?ptf0 ptf7?ptf0 address: $0441 bit 7654321bit 0 read: ptg7 ptg6 ptg5 ptg4 ptg3 ptg2 ptg1 ptg0 write: reset: unaffected by reset alternate function: ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 figure 13-23. port g data register (ptg) read ddrf ($0444) write ddrf ($0444) reset write ptf ($0440) read ptd ($0440) ptfx ddrfx ptfx internal data bus port g mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 187 ptg7?ptg0 ? port g data bits these read/write bits are software-programmable. da ta direction of each port g pin is under the control of the corresponding bit in data direction regi ster g. reset has no effect on port g data. ad23?ad16 ? analog-to-digital input bits ad23?ad16 are pins used for the input channels to the analog-to-digital converter module. the channel select bits in the adc status and control register define which port g pin will be used as an adc input and overrides any control from the port i/o logic by forcing that pin as the input to the analog circuitry. note care must be taken when reading port g while applying analog voltages to ad23?ad16 pins. if the appropriate adc channel is not enabled, excessive current drain may occur if analog voltages are applied to the ptgx/adx pin, while ptg is read as a digital input during the cpu read cycle. those ports not selected as analog input channels are considered digital i/o ports. 13.9.2 data dir ection register g data direction register g (ddrg) determines whether each port g pin is an input or an output. writing a 1 to a ddrg bit enables the output buffer for the corresponding port g pin; a 0 disables the output buffer. ddrg7?ddrg0 ? data direction register g bits these read/write bits control port g data direction. reset clears ddrg7?ddrg0], configuring all port g pins as inputs. 1 = corresponding port g pin configured as output 0 = corresponding port g pin configured as input note avoid glitches on port g pins by writing to the port g data register before changing data direction regist er g bits from 0 to 1. figure 13-25 shows the port g i/o logic. when bit ddrgx is a 1, reading ad dress $0441 reads the ptgx data latch. when bit ddrgx is a 0, reading address $0441 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 13-8 summarizes the operation of the port g pins. address: $0445 bit 7654321bit 0 read: ddrg7 ddrg6 ddrg5 ddrg4 ddrg3 ddrg2 ddrg1 ddrg0 write: reset:00000000 figure 13-24. data direction register g (ddrg) input/output (i/o) ports mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 188 freescale semiconductor figure 13-25. port g i/o circuit table 13-8. port g pin functions ddrg bit ptg bit i/o pin mode accesses to ddrg accesses to ptg read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrg7?ddrg0 pin ptg7?ptg0 (3) 3. writing affects data register, but does not affect input. 1 x output ddrg7?ddrg0 ptg7?ptg0 ptg7?ptg0 read ddrg ($0445) write ddrg ($0445) reset write ptg ($0441) read ptg ($0441) ptgx ddrgx ptgx internal data bus mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 189 chapter 14 enhanced serial communications interface (esci) module 14.1 introduction the enhanced serial communications interface (esc i) module allows asynchronous communications with peripheral devices and other microcontroller units (mcu). 14.2 features features include: ? full-duplex operation ? standard mark/space non-retu rn-to-zero (nrz) format ? programmable baud rates ? programmable 8-bit or 9-bit character length ? separately enabled transmitter and receiver ? separate receiver and transmitter centra l processor unit (cpu) interrupt requests ? programmable transmitter output polarity ? two receiver wakeup methods: ? idle line wakeup ? address mark wakeup ? interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error ? receiver framing error detection ? hardware parity checking ? 1/16 bit-time noise detection enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 190 freescale semiconductor figure 14-1. block diagram highlighting esci block and pins single breakpoint break module system integration module programmable timebase module monitor mode entry serial peripheral 6-channel timer interface module dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash ? 62,078 bytes user ram ? 2048 bytes monitor rom user flash vector space ? 52 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 rst (1) irq (1) interface module interrupt module computer operating properly module pta7/kbd7/ad15? 10-bit analog-to-digital converter module ptc6 (2) ptc5 (2) ptc4 (2, 3) ptc3 (2, 3) ptc2 (2, 3) ptc1/can rx (2, 3) ptc0/can tx (2, 3) ptd7/t2ch1 (2) ptd6/t2ch0 (2) ptd5/t1ch1 (2) ptd4/t1ch0 (2) ptd3/spsck (2) ptd2/mosi (2) ptd1/miso (2) ptd0/ss /mclk (2) pte1/rxd pte0/txd 2-channel timer interface module enhanced serial interface module security module power-on reset module memory map module configuration register 1?2 module power v ss v dd v ssa v dda 1. pin contains in tegrated pullup device. 2. ports are software configurable with pullup device if input port or pullup/pulldow n device for keyboard input. 3. higher current drive port pins v ddad /v refh v ssad /v refl pte5?pte2 communications clock generator module cgmxfc phase locked loop 1?8 mhz oscillator portb ddrb ptb7/ad7? portf ddrf ptf7/t2ch5 module portg ddrg ptg7/ad23? ptf6/t2ch4 ptf5/t2ch3 ptf4/t2ch2 ptf3?pft0 (3) mscan module pta0/kbd0/ad8 (2) ptb0/ad0 ptg0/ad16 pin name conventions mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 191 14.3 pin name conventions the generic names of the esci input/output (i/o) pins are: ? rxd (receive data) ? txd (transmit data) esci i/o lines are implemented by s haring parallel i/o port pins. the full name of an esci input or output reflects the name of the shared port pin. table 14-1 shows the full names and the generic names of the esci i/o pins. the generic pin names appear in the text of this section. 14.4 functional description figure 14-3 shows the structure of the esci module. t he esci allows full-duplex, asynchronous, nrz serial communication between the mcu and remote dev ices, including other mcus. the transmitter and receiver of the esci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the esci, writes the data to be transmitted, and processes received data. the baud rate clock source for the esci can be se lected via the configuration bit, scibdsrc, of the config2 register ($001e) for reference, a summary of the esci module input/output registers is provided in figure 14-4 . 14.4.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 14-2 . figure 14-2. sci data formats table 14-1. pin name conventions generic pin names rxd txd full pin names pte1/rxd pte0/txd bit 5 bit 0 bit 1 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity or data bit parity or data bit next start bit next start bit stop bit stop bit 8-bit data format (bit m in scc1 clear) 9-bit data format (bit m in scc1 set) start bit start bit enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 192 freescale semiconductor figure 14-3. esci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 orie feie peie bkf rpf esci data receive shift register esci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register transmitter interrupt control receiver interrupt control error interrupt control control ensci loops ensci internal bus txinv loops 4 16 pre- scaler baud rate generator scibdsrc rxd txd arbiter sci_txd rxd linr lint bus clock aclk bit in sciactl sl sci_clk enhanced prescaler sl from config2 bus cgmxclk clock sl = 1 -> sci_clk = busclk sl = 0 -> sci_clk = cgmxclk functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 193 addr.register name bit 7654321bit 0 $0009 esci prescaler register (scpsc) see page 214. read: pds2 pds1 pds0 pssb4 pssb3 pssb2 pssb1 pssb0 write: reset:00000000 $000a esci arbiter control register (sciactl) see page 217. read: am1 alost am0 aclk afin arun arovfl ard8 write: reset:00000000 $000b esci arbiter data register (sciadat) see page 218. read: ard7 ard6 ard5 ard4 ard3 ard2 ard1 ard0 write: reset:00000000 $0013 esci control register 1 (scc1) see page 204. read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0014 esci control register 2 (scc2) see page 206. read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 esci control register 3 (scc3) see page 208. read: r8 t8 r r orie neie feie peie write: reset:u0000000 $0016 esci status register 1 (scs1) see page 209. read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 esci status register 2 (scs2) see page 211. read:000000bkfrpf write: reset:00000000 $0018 esci data register (scdr) see page 212. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 esci baud rate register (scbr) see page 212. read: lint linr scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved figure 14-4. esci i/o register summary enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 194 freescale semiconductor 14.4.2 transmitter figure 14-5 shows the structure of the sci transmitter and the registers are summarized in figure 14-4 . the baud rate clock source for the esci can be selected via the configuration bit, scibdsrc. figure 14-5. esci transmitter 14.4.2.1 character length the transmitter can accommodate either 8-bit or 9- bit data. the state of the m bit in esci control register 1 (scc1) determines character length. when tr ansmitting 9-bit data, bit t8 in esci control register 3 (scc3) is the ninth bit (bit 8). 14.4.2.2 character transmission during an esci transmission, the transmit shift regist er shifts a character out to the txd pin. the esci data register (scdr) is the write-only buffer between t he internal data bus and the transmit shift register. pen pty h876543210l 11-bit transmit stop start t8 scte sctie tcie sbk tc parity generation msb esci data register load from scdr shift enable preamble (all ones) break (all zeros) transmitter control logic shift register tc sctie tcie scte m ensci loops te txinv internal bus 4 pre- scaler scp1 scp0 scr1 scr2 scr0 baud divider 16 sci_txd pre- scaler pds1 pds2 pds0 pssb3 pssb4 pssb2 pssb1 pssb0 lint transmitter cpu interrupt request cgmxclk or bus clock functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 195 to initiate an esci transmission: 1. enable the esci by writing a 1 to the enable esci bit (ensci) in esci control register 1 (scc1). 2. enable the transmitter by writing a 1 to the trans mitter enable bit (te) in esci control register 2 (scc2). 3. clear the esci transmitter empty bit (scte) by first reading esci status register 1 (scs1) and then writing to the scdr. for 9-bit data, also write the t8 bit in scc3. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, transmitter control logi c automatically loads the tran smit shift register with a preamble of 1s. after the preamble shifts out, cont rol logic transfers the s cdr data into the transmit shift register. a 0 start bit automatically goes into the least significant bit (lsb) position of the transmit shift register. a 1 stop bit goes into the most significant bit (msb) position. the esci transmitter empty bit, scte, in scs1 beco mes set when the scdr transfers a byte to the transmit shift register. the scte bi t indicates that the scdr can accept new data from the internal data bus. if the esci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter cpu interrupt request. when the transmit shift register is not transmitting a c haracter, the txd pin goes to the idle condition, high. if at any time software clears the ensc i bit in esci control register 1 (scc1), the transmitter and receiver relinquish control of the port e pins. 14.4.2.3 break characters writing a 1 to the send break bit, sbk, in scc2 loads the transmit shift register with a break character. for txinv = 0 (output not inverted), a transmitted break character contains all 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1 and the linr bits in scbr. as long as sbk is at 1, transmitter logic conti nuously loads break charac ters into the transmit shift register. after software clears the sbk bit, the shift register finis hes transmitting the last break character and then transmits at least one 1. the automatic 1 at the end of a break character guarantees the recognition of the start bit of the next character. when linr is cleared in scbr, the esci recognizes a break character when a start bit is followed by eight or nine 0 data bits and a 0 where the stop bit should be, resulting in a total of 10 or 11 consecutive 0 data bits. when linr is set in scbr, the esci recognizes a break character when a start bit is followed by 9 or 10 0 data bits and a 0 where the stop bit shoul d be, resulting in a total of 11 or 12 consecutive 0 data bits. receiving a break character has these effects on esci registers: ? sets the framing error bit (fe) in scs1 ? sets the esci receiver full bit (scrf) in scs1 ? clears the esci data register (scdr) ? clears the r8 bit in scc3 ? sets the break flag bit (bkf) in scs2 ? may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 196 freescale semiconductor 14.4.2.4 idle characters for txinv = 0 (output not inverted), a transmitted idle character contains all 1s and has no start, stop, or parity bit. idle character length depends on the m bi t in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a transmission, the txd pin become s idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. note when a break sequence is followed immedi ately by an idle character, this sci design exhibits a condition in wh ich the break character length is reduced by one half bit time. in this instance, the break sequence will consist of a valid start bit, eight or ni ne data bits (as defined by the m bit in scc1) of 0 and one half data bit length of 0 in the stop bit position followed immediately by the idle character. to ensure a break character of the proper length is transmitted, always queue up a byte of data to be transmitted while the final break sequence is in progress. when queueing an idle character, return the te bit to 1 before the stop bit of the current character shifts out to the txd pin. setting te after the stop bit appears on txd causes da ta previously written to the scdr to be lost. a good time to toggle the te bit for a queued idle character is when the scte bit becomes set and just before writing the next byte to the scdr. 14.4.2.5 inversion of transmitted output the transmit inversion bit (txinv) in esci control r egister 1 (scc1) reverses the polarity of transmitted data. all transmitted values including idle, break, star t, and stop bits, are inverted when txinv is at 1. see 14.8.1 esci control register 1 . 14.4.2.6 transmitter interrupts these conditions can generate cpu interrupt requests from the esci transmitter: ? esci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request. setting the esci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. ? transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests. 14.4.3 receiver figure 14-6 shows the structure of the esci receiver. the receiver i/o registers are summarized in figure 14-4 . functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 197 figure 14-6. esci receiver block diagram 14.4.3.1 character length the receiver can accommodate either 8-bit or 9-bit dat a. the state of the m bit in esci control register 1 (scc1) determines character length. when receiving 9-bi t data, bit r8 in esci control register 3 (scc3) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). all ones all zeros m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery or orie nf neie fe feie pe peie scrie scrf ilie idle wakeup logic parity checking msb esci data register r8 scrie ilie rwu scrf idle internal bus pre- scaler baud divider 4 16 scp1 scp0 scr1 scr2 scr0 rxd pre- scaler pds1 pds2 pds0 pssb3 pssb4 pssb2 pssb1 pssb0 linr orie neie feie peie or nf fe pe cgmxclk or bus clock cpu interrupt request error cpu interrupt request enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 198 freescale semiconductor 14.4.3.2 character reception during an esci reception, the receive shift register sh ifts characters in from the rxd pin. the esci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive sh ift register, the data portion of the character transfers to the scdr. the esci receiver full bit, scrf, in esci status register 1 (scs1) becomes set, indicating that the received byte can be read. if the esci rece ive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request. 14.4.3.3 data sampling the receiver samples the rxd pin at the rt clock rate . the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at these times (see figure 14-7 ): ? after every start bit ? after the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid 0) to locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s. when the falling edge of a possible start bit oc curs, the rt clock begins to count to 16. figure 14-7. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 14-2 summarizes the results of the start bit verification samples. table 14-2. start bit verification rt3, rt5, and rt7 samples sta rt bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb rxd functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 199 if start bit verification is not successful, the rt cl ock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-3 summarizes the results of the data bit samples. note the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are 1s following a successful start bit verification, the noi se flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-4 summarizes the results of the stop bit samples. 14.4.3.4 framing errors if the data recovery logic does not detect a 1 where t he stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. a break character also sets the fe bit because a break character has no stop bit. the fe bit is set at t he same time that the scrf bit is set. table 14-3. data bit recovery rt8, rt9, and rt10 samples d ata bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 14-4. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 200 freescale semiconductor 14.4.3.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bi t data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within char acters corrects misalignments between transmitter bit times and receiver bit times. slow data tolerance figure 14-8 shows how much a slow received characte r can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 14-8. slow data for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 14-8 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is: for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 14-8 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles + 3 rt cycl es = 163 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 ? 154 ------------------------- - 100 4.54% = 170 163 ? 170 ------------------------- - 100 4.12% = functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 201 fast data tolerance figure 14-9 shows how much a fast received characte r can be misaligned without causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but is still there for the stop bit data samples at rt8, rt9, and rt10. figure 14-9. fast data for an 8-bit character, data sampling of the stop bit takes the receiver 9bittimes 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 14-9 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 14-9 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: 14.4.3.6 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bi t in scc1, either of two conditio ns on the rxd pin can bring the receiver out of the standby state: 1. address mark ? an address mark is a 1 in th e msb position of a received character. when the wake bit is set, an address mark wakes the receiv er from the standby st ate by clearing the rwu bit. the address mark also sets the esci receiver full bit, scrf. software can then compare the character containing the address mark to the user -defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. 2. idle input line condition ? when the wake bit is cl ear, an idle character on the rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 ? 154 ------------------------- - 100 3.90%. = 170 176 ? 170 ------------------------- - 100 3.53%. = enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 202 freescale semiconductor does not set the receiver idle bit, idle, or the esci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting 1s as idle character bits after the start bit or after the stop bit. note with the wake bit clear, setting the rwu bit after the rxd pin has been idle will cause the receiver to wake up. 14.4.3.7 receiver interrupts these sources can generate cpu interrupt requests from the esci receiver: ? esci receiver full (scrf) ? the scrf bit in sc s1 indicates that the receive shift register has transferred a character to the scdr. scrf can generate a receiver cpu interrupt request. setting the esci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. ? idle input (idle) ? the idle bit in scs1 indicates that 10 or 11 consecutive 1s shifted in from the rxd pin. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. 14.4.3.8 error interrupts these receiver error flags in scs1 can generate cpu interrupt requests: ? receiver overrun (or) ? the or bit indicates t hat the receive shift register shifted in a new character before the previous c haracter was read from the scdr. the previous character remains in the scdr, and the new character is lost. th e overrun interrupt enable bit, orie, in scc3 enables or to generate esci error cpu interrupt requests. ? noise flag (nf) ? the nf bit is set when t he esci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate esci error cpu interrupt requests. ? framing error (fe) ? the fe bit in scs1 is set when a 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate esci error cpu interrupt requests. ? parity error (pe) ? the pe bit in scs1 is set when the esci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to generate esci error cpu interrupt requests. 14.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 14.5.1 wait mode the esci module remains active in wait mode. any enabled cpu interrupt request from the esci module can bring the mcu out of wait mode. if esci module functions are not required during wait mode, reduce power consum ption by disabling the module before executing the wait instruction. esci during break mo dule interrupts mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 203 14.5.2 stop mode the esci module is inactive in stop mode. the stop instruction does not affect esci register states. esci module operation resumes after the mcu exits stop mode. because the internal clock is i nactive during stop mode, entering stop mode during an esci transmission or reception results in invalid data. 14.6 esci during br eak module interrupts the bcfe bit in the break flag control register (sbfcr) enables software to clear status bits during the break state. see 20.2 break module (brk) . to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 14.7 i/o signals port e shares two of its pins with th e esci module. the two esci i/o pins are: ? pte0/txd ? transmit data ? pte1/rxd ? receive data 14.7.1 pte0/txd (transmit data) the pte0/txd pin is the serial data output from the esci transmitter. the esci shares the pte0/txd pin with port e. when the esci is enabled, the pte0/txd pin is an output regardless of the state of the ddre0 bit in data direction register e (ddre). 14.7.2 pte1/rxd (receive data) the pte1/rxd pin is the serial data input to the es ci receiver. the esci shares the pte1/rxd pin with port e. when the esci is enabled, the pte1/rxd pin is an input regardless of the state of the ddre1 bit in data direction register e (ddre). 14.8 i/o registers these i/o registers control and monitor esci operation: ? esci control register 1, scc1 ? esci control register 2, scc2 ? esci control register 3, scc3 ? esci status register 1, scs1 ? esci status register 2, scs2 ? esci data register, scdr enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 204 freescale semiconductor ? esci baud rate register, scbr ? esci prescaler register, scpsc ? esci arbiter control register, sciactl ? esci arbiter data register, sciadat 14.8.1 esci control register 1 esci control register 1 (scc1): ? enables loop mode operation ? enables the esci ? controls output polarity ? controls character length ? controls esci wakeup method ? controls idle character detection ? enables parity function ? controls parity type loops ? loop mode select bit this read/write bit enables loop mode operation. in loop mode the rxd pin is disconnected from the esci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable esci bit this read/write bit enables the esci and the esci baud rate generator. clearing ensci sets the scte and tc bits in esci status register 1 and disabl es transmitter interrupts. reset clears the ensci bit. 1 = esci enabled 0 = esci disabled txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note setting the txinv bit invert s all transmitted values including idle, break, start, and stop bits. address: $0013 bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 14-10. esci control register 1 (scc1) i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 205 m ? mode (character length) bit this read/write bit determines whether esci characters are eight or nine bits long (see table 14-5 ).the ninth bit can serve as a receiver wakeup signal or as a parity bit. reset clears the m bit. 1 = 9-bit esci characters 0 = 8-bit esci characters wake ? wakeup condition bit this read/write bit determines which condition wakes up the esci: a 1 (address mark) in the msb position of a received c haracter or an idle condition on t he rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit determines when the esci starts counting 1s as idle character bits. the counting begins either after the start bit or after the stop bi t. if the count begins after the start bit, then a string of 1s preceding the stop bit may cause false recognit ion of an idle character. beginning the count after the stop bit avoids false idle character recognition , but requires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit pen ? parity enable bit this read/write bit enables the esci parity function (see table 14-5 ). when enabled, the parity function inserts a parity bit in the msb position (see table 14-3 ). reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled pty ? parity bit this read/write bit determines whether the esc i generates and checks for odd parity or even parity (see table 14-5 ). reset clears the pty bit. 1 = odd parity 0 = even parity note changing the pty bit in the middle of a transmission or reception can generate a parity error. table 14-5. character format selection control bits character format m pen:pty start bits data bits pa rity stop bits character length 0 0 x 1 8 none 1 10 bits 1 0 x 1 9 none 1 11 bits 0 1 0 1 7 even 1 10 bits 0 1 1 1 7 odd 1 10 bits 1 1 0 1 8 even 1 11 bits 1 1 1 1 8 odd 1 11 bits : enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 206 freescale semiconductor 14.8.2 esci control register 2 esci control register 2 (scc2): ? enables these cpu interrupt requests: ? scte bit to generate transmitter cpu interrupt requests ? tc bit to generate transmitter cpu interrupt requests ? scrf bit to generate receiver cpu interrupt requests ? idle bit to generate receiver cpu interrupt requests ? enables the transmitter ? enables the receiver ? enables esci wakeup ? transmits esci break characters sctie ? esci transmit interrupt enable bit this read/write bit enables the scte bit to generat e esci transmitter cpu interrupt requests. setting the sctie bit in scc2 enables the scte bit to generate cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ? transmission complete interrupt enable bit this read/write bit enables the tc bit to generate esci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? esci receive interrupt enable bit this read/write bit enables the scrf bit to generate esci receiver cpu interrupt requests. setting the scrie bit in scc2 enables the scrf bit to generate cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to generate esci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests address: $0014 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 14-11. esci control register 2 (scc2) i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 207 te ? transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 1s from the transmit shift register to the txd pin. if softw are clears the te bit, the transmitter completes any transmission in progress before the txd returns to the idle condition (high). clearing and then setting te during a transmission queues an id le character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note writing to the te bit is not allowed when the enable esci bit (ensci) is clear. ensci is in esci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clea ring the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note writing to the re bit is not allowed when the enable esci bit (ensci) is clear. ensci is in esci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle i nput or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting and then clearing this read/writ e bit transmits a break character followed by a 1. the 1 after the break character guarantees recogni tion of a valid start bit. if sbk remains set, the transmitter continuously transmits break c haracters with no 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break characters being transmitted note do not toggle the sbk bit immediately a fter setting the scte bit. toggling sbk before the preamble begins caus es the esci to send a break character instead of a preamble. 14.8.3 esci control register 3 esci control register 3 (scc3): ? stores the ninth esci data bit received and the ninth esci data bit to be transmitted. ? enables these interrupts: ? receiver overrun ? noise error ? framing error ? parity error enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 208 freescale semiconductor r8 ? received bit 8 when the esci is receiving 9-bit characters, r8 is the read-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other 8 bits. when the esci is receiving 8-bit characters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the esci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift regi ster at the same time that the scdr is loaded into the transmit shift register. reset clears the t8 bit. orie ? receiver overrun interrupt enable bit this read/write bit enables esci error cpu interrupt requests generated by the receiver overrun bit, or. reset clears orie. 1 = esci error cpu interrupt requests from or bit enabled 0 = esci error cpu interrupt requests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enables esci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = esci error cpu interrupt requests from ne bit enabled 0 = esci error cpu interrupt requests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enables esci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = esci error cpu interrupt requests from fe bit enabled 0 = esci error cpu interrupt requests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables esci receiver cpu interrupt requests generated by the parity error bit, pe. reset clears peie. 1 = esci error cpu interrupt requests from pe bit enabled 0 = esci error cpu interrupt requests from pe bit disabled address: $0015 bit 7654321bit 0 read: r8 t8 r r orie neie feie peie write: reset:u0000000 = unimplemented r = reserved u = unaffected figure 14-12. esci control register 3 (scc3) i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 209 14.8.4 esci status register 1 esci status register 1 (scs1) contai ns flags to signal these conditions: ? transfer of scdr data to transmit shift register complete ? transmission complete ? transfer of receive shift register data to scdr complete ? receiver input idle ? receiver overrun ? noisy data ? framing error ? parity error scte ? esci transmitter empty bit this clearable, read-only bit is set when the scdr tr ansfers a character to the transmit shift register. scte can generate an esci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an esci transmitter cpu interrupt re quest. in normal operation, clear the scte bit by reading scs1 with scte set and then writing to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register tc ? transmission complete bit this read-only bit is set when the scte bit is se t, and no data, preamble, or break character is being transmitted. tc generates an esci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is cleared automatically when data, preamble , or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of lat ency between queueing data, preamble, and break and the transmission actually starti ng. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? esci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the esci data register. scrf can generate an esci receiver cpu interrupt request. when the scrie bit in scc2 is set the scrf generates a cpu interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr address: $0016 bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 14-13. esci status register 1 (scs1) enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 210 freescale semiconductor idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. idle generates an esci receiver cpu interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit befo re an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character mu st again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or id le since the idle bit was cleared) or ? receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an esci error cpu interrupt request if the orie bit in scc3 is also set. the da ta in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an ove rrun to occur between reads of sc s1 and scdr in the flag-clearing sequence. figure 14-14 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearin g sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-clearing sequence reads byte 3 in the scdr instead of byte 2. figure 14-14. flag clearing sequence byte 1 normal flag clearing sequence scrf = 1 scrf = 1 byte 2 byte 3 byte 4 scrf = 0 scrf = 1 scrf = 0 scrf = 0 byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 read scs1 scrf = 1 or = 0 read scs1 scrf = 1 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 1 read scdr byte 2 read scdr byte 3 read scs1 scrf = 1 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 1 read scdr byte 3 i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 211 in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. nf ? receiver noise flag bit this clearable, read-only bit is set when the esc i detects noise on the rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is al so set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected fe ? receiver framing error bit this clearable, read-only bit is set when a 0 is accepted as the stop bit. fe generates an esci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected pe ? receiver parity error bit this clearable, read-only bit is set when the esci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected 14.8.5 esci status register 2 esci status register 2 (scs2) contai ns flags to signal these conditions: ? break character detected ? incoming data bkf ? break flag bit this clearable, read-only bit is set when the esci detects a break character on the rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become se t again only after 1s agai n appear on the rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected address: $0017 bit 7654321bit 0 read:000000bkfrpf write: reset:00000000 = unimplemented figure 14-15. esci status register 2 (scs2) enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 212 freescale semiconductor rpf ? reception in progress flag bit this read-only bit is set when the receiver detects a 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. polling rpf before disabling the esci module or entering stop mode can show whethe r a reception is in progress. 1 = reception in progress 0 = no reception in progress 14.8.6 esci data register the esci data register (scdr) is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the esci data register. r7/t7:r0/t0 ? receive/transmit data bits reading address $0018 accesses the read-only rece ived data bits, r7:r0. writing to address $0018 writes the data to be transmitted, t7:t0. re set has no effect on the esci data register. note do not use read-modify-write instructions on the esci data register. 14.8.7 esci baud rate register the esci baud rate register (scbr) together with the esci prescaler register selects the baud rate for both the receiver and the transmitter. note there are two prescalers available to adjust the baud rate. one in the esci baud rate register and one in the esci prescaler register. lint ? lin transmit enable this read/write bit selects the enhanced esci features for the local interconnect network (lin) protocol as shown in table 14-6 . reset clears lint. address: $0018 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 14-16. esci data register (scdr) address: $0019 bit 7654321bit 0 read: lint linr scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 r = reserved figure 14-17. esci baud rate register (scbr) i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 213 linr ? lin receiver bits this read/write bit selects the enhanced esci features for the local interconnect network (lin) protocol as shown in table 14-6 . reset clears linr. in lin (version 1.2) systems, the master node transmits a break charac ter which will appear as 11.05?14.95 dominant bits to the slave node. a dat a character of 0x00 sent from the master might appear as 7.65?10.35 dominant bit times. this is due to the oscillator tolerance requirement that the slave node must be within 15% of the master node's oscillator. since a slave node cannot know if it is running faster or slower than the master node (pri or to synchronization), the linr bit allows the slave node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits. the break symbol length must be verified in software in any case, but the linr bit serves as a filter, preventing false detections of break characte rs that are really 0x00 data characters. scp1 and scp0 ? esci baud rate register prescaler bits these read/write bits select the baud rate register prescaler divisor as shown in table 14-7 . reset clears scp1 and scp0. scr2?scr0 ? esci baud rate select bits these read/write bits select the esci baud rate divisor as shown in table 14-8 . reset clears scr2?scr0. table 14-6. esci lin control bits lint linr m functionality 0 0 x normal esci functionality 0 1 0 11-bit break detect enabled for lin receiver 0 1 1 12-bit break detect enabled for lin receiver 1 0 0 13-bit generation enabled for lin transmitter 1 0 1 14-bit generation enabled for lin transmitter 1 1 0 11-bit break detect/13-bit generation enabled for lin 1 1 1 12-bit break detect/14-bit generation enabled for lin table 14-7. esci baud rate prescaling scp[1:0] baud rate register prescaler divisor (bpd) 00 1 01 3 10 4 11 13 table 14-8. esci baud rate selection scr[2:1:0] baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 214 freescale semiconductor 14.8.8 esci prescaler register the esci prescaler register (scpsc) together with the esci baud rate register selects the baud rate for both the receiver and the transmitter. note there are two prescalers available to adjust the baud rate. one in the esci baud rate register and one in the esci prescaler register. ; pds2?pds0 ? prescaler divisor select bits these read/write bits select the prescaler divisor as shown in table 14-9 . reset clears pds2?pds0. note the setting of ?000? will bypass not only this prescaler but also the prescaler divisor fine adjust (pdfa). it is not recommended to bypass the prescaler while ensci is set, because the switching is not glitch free. pssb4?pssb0 ? clock insertion select bits these read/write bits select the number of clocks inserted in each 32 output cycle frame to achieve more timing resolution on the average prescaler frequency as shown in table 14-10 . reset clears pssb4?pssb0. address: $0009 bit 7654321bit 0 read: pds2 pds1 pds0 pssb4 pssb3 pssb2 pssb1 pssb0 write: reset:00000000 figure 14-18. esci prescaler register (scpsc) table 14-9. esci prescaler division ratio pds[2:1:0] prescaler divisor (pd) 0 0 0 bypass this prescaler 001 2 010 3 011 4 100 5 101 6 110 7 111 8 table 14-10. esci prescaler divisor fine adjust pssb[4:3:2:1:0] prescaler di visor fine adjust (pdfa) 00000 0/32 = 0 00001 1/32 = 0.03125 00010 2/32 = 0.0625 00011 3/32 = 0.09375 0 0 1 0 0 4/32 = 0.125 i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 215 use the following formula to calculate the esci baud rate: where: frequency of the sci clock source = f bus or cgmxclk (selected by scibdsrc in the config2 register) bpd = baud rate register prescaler divisor bd = baud rate divisor pd = prescaler divisor pdfa = prescaler divisor fine adjust table 14-11 shows the esci baud rates that can be generated with a 4.9152-mhz bus frequency. 00101 5/32 = 0.15625 00110 6/32 = 0.1875 00111 7/32 = 0.21875 0 1 0 0 0 8/32 = 0.25 01001 9/32 = 0.28125 0 1 0 1 0 10/32 = 0.3125 0 1 0 1 1 11/32 = 0.34375 0 1 1 0 0 12/32 = 0.375 0 1 1 0 1 13/32 = 0.40625 0 1 1 1 0 14/32 = 0.4375 0 1 1 1 1 15/32 = 0.46875 10000 16/32 = 0.5 1 0 0 0 1 17/32 = 0.53125 1 0 0 1 0 18/32 = 0.5625 1 0 0 1 1 19/32 = 0.59375 1 0 1 0 0 20/32 = 0.625 1 0 1 0 1 21/32 = 0.65625 1 0 1 1 0 22/32 = 0.6875 1 0 1 1 1 23/32 = 0.71875 1 1 0 0 0 24/32 = 0.75 1 1 0 0 1 25/32 = 0.78125 1 1 0 1 0 26/32 = 0.8125 1 1 0 1 1 27/32 = 0.84375 1 1 1 0 0 28/32 = 0.875 1 1 1 0 1 29/32 = 0.90625 1 1 1 1 0 30/32 = 0.9375 1 1 1 1 1 31/32 = 0.96875 table 14-10. esci prescaler divisor fine adjust (continued) pssb[4:3:2:1:0] prescaler di visor fine adjust (pdfa) frequency of the sci clock source 64 x bpd x bd x (pd + pdfa) baud rate = enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 216 freescale semiconductor table 14-11. esci baud rate selection examples pds[2:1:0] pssb[4:3:2:1:0] scp[1:0] prescaler divisor (bpd) scr[2:1:0] baud rate divisor (bd) baud rate (f bus = 4.9152 mhz) 000 xxxxx 00 1 000 1 76,800 111 00000 00 1 000 1 9600 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 9562.65 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 9525.58 1 1 1 1 1 1 1 1 0 0 1 0 0 0 1 8563.07 000 xxxxx 00 1 001 2 38,400 000 xxxxx 00 1 010 4 19,200 000 xxxxx 00 1 011 8 9600 000 xxxxx 00 1 100 16 4800 000 xxxxx 00 1 101 32 2400 000 xxxxx 00 1 110 64 1200 000 xxxxx 00 1 111 128 600 000 xxxxx 01 3 000 1 25,600 000 xxxxx 01 3 001 2 12,800 000 xxxxx 01 3 010 4 6400 000 xxxxx 01 3 011 8 3200 000 xxxxx 01 3 100 16 1600 000 xxxxx 01 3 101 32 800 000 xxxxx 01 3 110 64 400 000 xxxxx 01 3 111 128 200 000 xxxxx 10 4 000 1 19,200 000 xxxxx 10 4 001 2 9600 000 xxxxx 10 4 010 4 4800 000 xxxxx 10 4 011 8 2400 000 xxxxx 10 4 100 16 1200 000 xxxxx 10 4 101 32 600 000 xxxxx 10 4 110 64 300 000 xxxxx 10 4 111 128 150 000 xxxxx 11 13 000 1 5908 000 xxxxx 11 13 001 2 2954 000 xxxxx 11 13 010 4 1477 000 xxxxx 11 13 011 8 739 000 xxxxx 11 13 100 16 369 000 xxxxx 11 13 101 32 185 000 xxxxx 11 13 110 64 92 000 xxxxx 11 13 111 128 46 esci arbiter mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 217 14.9 esci arbiter the esci module comprises an arbiter module designed to support software for communication tasks as bus arbitration, baud rate recovery and break time det ection. the arbiter module consists of an 9-bit counter with 1-bit overflow and control logic. the cpu can control operation mode via the esci arbiter control register (sciactl). 14.9.1 esci arbite r control register am1 and am0 ? arbiter mode select bits these read/write bits select the mode of the arbiter module as shown in table 14-12 . reset clears am1 and am0. alost ? arbitration lost flag this read-only bit indicates loss of arbitration. clear alost by writing a 0 to am1. reset clears alost. aclk ? arbiter counter clock select bit this read/write bit selects the arbiter counter clock source. reset clears aclk. 1 = arbiter counter is clocked with one half of t he esci input clock generated by the esci prescaler 0 = arbiter counter is clocked wi th the bus clock divided by four note for aclk = 1, the arbiter input clock is driven from the esci prescaler. the prescaler can be clocked by either the bus clock or cgmxclk depending on the state of the scibdsrc bit in config2. afin? arbiter bit time measurement finish flag this read-only bit indicates bit ti me measurement has finished. clea r afin by writing any value to sciactl. reset clears afin. 1 = bit time measurement has finished 0 = bit time measurement not yet finished address: $000a bit 7654321bit 0 read: am1 alost am0 aclk afin arun arovfl ard8 write: reset:00000000 = unimplemented figure 14-19. esci arbiter control register (sciactl) table 14-12. esci arbiter selectable modes am[1:0] esci arbiter mode 0 0 idle / counter reset 0 1 bit time measurement 1 0 bus arbitration 1 1 reserved / do not use enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 218 freescale semiconductor arun? arbiter counter running flag this read-only bit in dicates the arbiter counter is running. reset clears arun. 1 = arbiter counter running 0 = arbiter counter stopped arovfl? arbiter counter overflow bit this read-only bit indicates an arbiter counter ov erflow. clear arovfl by writing any value to sciactl. writing 0s to am1 and am0 resets the counter keeps it in this idle state. reset clears arovfl. 1 = arbiter counter overflow has occurred 0 = no arbiter counter overflow has occurred ard8? arbiter counter msb this read-only bit is the msb of the 9-bit arbiter c ounter. clear ard8 by writing any value to sciactl. reset clears ard8. 14.9.2 esci arbite r data register ard7?ard0 ? arbiter least significant counter bits these read-only bits are the eight lsbs of the 9-bi t arbiter counter. clear ard7?ard0 by writing any value to sciactl. writing 0s to am1 and am0 permanent ly resets the counter and keeps it in this idle state. reset clears ard7?ard0. 14.9.3 bit time measurement two bit time measurement modes, described here, are available acco rding to the state of aclk. 1. aclk = 0 ? the counter is clocked with the bus clock divided by four. the counter is started when a falling edge on the rxd pin is detected. the counter will be stopped on the next falling edge. arun is set while the counter is running, afin is set on the second falling edge on rxd (for instance, the counter is stopped). this mode is used to recover the received baud rate. see figure 14-21 . 2. aclk = 1 ? the counter is clocked with one hal f of the esci input clock generated by the esci prescaler. the counter is started when a 0 is detected on rxd (see figure 14-22 ). a 0 on rxd on enabling the bit time measurement with aclk = 1 leads to immediate start of the counter (see figure 14-23 ). the counter will be stopped on the next rising edge of rxd. this mode is used to measure the length of a received break. 14.9.4 arbitration mode if am[1:0] is set to 10, the arbiter module operates in arbitration mode. on every rising edge of sci_txd (output of the esci module, internal chip signal), the counter is started. when the counter reaches $38 (aclk = 0) or $08 (aclk = 1), rxd is statically sensed. if in this case, rxd is sensed low (for example, address: $000b bit 7654321bit 0 read: ard7 ard6 ard5 ard4 ard3 ard2 ard1 ard0 write: reset:00000000 = unimplemented figure 14-20. esci arbiter data register (sciadat) esci arbiter mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 219 another bus is driving the bus dominant) alost is se t. as long as alost is set, the txd pin is forced to 1, resulting in a seized transmission. if sci_txd senses 0 without having sensed a 0 befor e on rxd, the counter will be reset, arbitration operation will be restarted after the next rising edge of sci_txd. figure 14-21. bit time measurement with aclk = 0 figure 14-22. bit time measurement with aclk = 1, scenario a figure 14-23. bit time measurement with aclk = 1, scenario b cpu writes sciactl counter starts, counter stops, measured time cpu reads result rxd with $20 arun = 1 afin = 1 out of sciadat cpu writes sciactl with $30 counter starts, arun = 1 counter stops, afin = 1 measured time cpu reads result out rxd of sciadat cpu writes sciactl counter starts, counter stops, measured time cpu reads result rxd out of sciadat afin = 1 arun = 1 with $30 enhanced serial communicatio ns interface (esci) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 220 freescale semiconductor mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 221 chapter 15 system integration module (sim) 15.1 introduction this section describes the system integration module (sim). together with the central processor unit (cpu), the sim controls all microcontroller unit (mcu) activities. a block diagram of the sim is shown in figure 15-1 . table 15-1 is a summary of the sim input/output (i/o) registers. the sim is a system state controller that coordinates cpu and exception timing. the sim is responsible for: ? bus clock generation and control for cpu and peripherals: ? stop/wait/reset/break entry and recovery ? internal clock control ? master reset control, including power-on reset (por) and computer operating properly (cop) timeout ? interrupt arbitration table 15-1 shows the internal signal names used in this section. table 15-1. signal name conventions signal name description cgmxclk buffered version of osc1 fr om clock generator module (cgm) cgmvclk pll output cgmout pll-based or osc1-based clock output from cgm module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal system integration module (sim) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 222 freescale semiconductor figure 15-1. sim block diagram stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to cgm) cgmout (from cgm) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cgmxclk (from cgm) 2 v dd internal pullup device forced monitor mode entry introduction mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 223 7 addr.register name bit 7654321bit 0 $fe00 break status register (bsr) see page 237. read: rrrrrr sbsw r write: note (1) reset:00000000 1. writing a 0 clears sbsw. $fe01 sim reset status register (srsr) see page 237. read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe03 break flag control register (bfcr) see page 238. read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) see page 231. read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) see page 233. read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) see page 233. read: if22 if32 if20 if19 if18 if17 if16 if15 write:rrrrrrrr reset:00000000 $fe07 interrupt status register 4 (int4) see page 233. read:000000if24if23 write:rrrrrrrr reset:00000000 = unimplemented r = reserved figure 15-2. sim i/o register summary system integration module (sim) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 224 freescale semiconductor 15.2 sim bus clock control and generation the bus clock generator provides system clock signa ls for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, cgmout, as shown in figure 15-3 . this clock originates from either an external oscillator or from the on-chip pll. figure 15-3. system clock signals 15.2.1 bus timing in user mode , the internal bus frequency is either the crys tal oscillator output (cgmxclk) divided by four or the pll output (cgmvclk) divided by four. 15.2.2 clock startup fr om por or lvi reset when the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inac tive phase until after the 4096 cgmxclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the bus clocks start upon completion of the timeout. 15.2.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt or rese t, the sim allows cgmxclk to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 32 cgmxclk cycles. see 15.6.2 stop mode. in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to s ee if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 2 bus clock generators sim sim counter simoscen oscillator (osc) osc2 osc1 phase-locked loop (pll) cgmxclk cgmrclk it12 cgmout to tbm,tim1,tim2, adc, mscan osceninstop from config to rest of chip it23 to rest of chip to mscan reset and system initialization mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 225 15.3 reset and s ystem initialization the mcu has these reset sources: ? power-on reset module (por) ? external reset pin (rst ) ? computer operating properly module (cop) ? low-voltage inhibit module (lvi) ? illegal opcode ? illegal address ? forced monitor mode entry reset (modrst) all of these resets produce the vector $fffe:$ffff ($fefe:$feff in monitor mode) and assert the internal reset signal (irst). irst causes all register s to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 15.4 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). see 15.7 sim registers. a reset immediately stops the operation of the instruction being executed. reset initializes certain control and status bits. reset selects cgmxclk divided by four as the bus clock. 15.3.1 external pin reset the rst pin circuit includes an internal pullu p device. pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for at least the minimum t rl time and no other reset sources are present. figure 15-4 shows the relative timing. figure 15-4. external reset timing 15.3.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow resetting of external peripherals. the internal re set continues to be asserted for an additional 32 cycles at which point the reset vector will be fetched. see figure 15-5 . an internal reset can be caused by an illegal address, illegal opcode, cop timeout, lvi, or por. see figure 15-6 . note for lvi or por resets, the sim c ycles through 4096 cgmxclk cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 15-5 . the cop reset is asynchronous to the bus clock. the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. rst iab pc vect h vect l cgmout system integration module (sim) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 226 freescale semiconductor figure 15-5. internal reset timing figure 15-6. sources of internal reset 15.3.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 + 32 cgmxclk cycles. thirty-two cgmxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, these events occur: ? a por pulse is generated. ? the internal reset signal is asserted. ? the sim enables cgmout. ? internal clocks to the cpu and modules are hel d inactive for 4096 cgmxclk cycles to allow stabilization of the oscillator. ?the rst pin is driven low during the oscillator stabilization time. ? the por bit of the sim reset status register (srsr) is set. 15.3.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of th e cop counter causes an internal reset and sets the cop bit in the sim reset stat us register (srsr) if the copd bit in the config1 register is cleared. the sim actively pulls down the rst pin for all internal reset sources. the cop module is disabled if the rst pin or the irq pin is held at v tst while the mcu is in monitor mode. during a break state, v tst on the rst pin disables the cop module. table 15-2. reset recovery reset recovery type actual number of cycles por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk illegal address rst illegal opcode rst coprst lvi por internal reset modrst reset and system initialization mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 227 figure 15-7. por recovery 15.3.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the config1 register is 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode re set. the sim actively pulls down the rst pin for all internal reset sources. 15.3.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped add ress does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. 15.3.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the v tripf voltage. the lvi bit in the sim reset status regist er (srsr) is set, and the external reset pin (rst ) is asserted if the lvipwrd and lvirstd bits in the config1 register are 0. the rst pin will be held low while the sim counter counts out 4096 + 32 cgmxclk cycles after v dd rises above v tripr . thirty-two cgmxclk cycles later, the cpu is released from rese t to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 15.3.2.6 monitor mode entry module reset (modrst) the monitor mode entry module reset (modrst) asserts its output to the sim when monitor mode is entered in the condition where the reset vectors are erased ($ff) (see 20.3.1.1 normal monitor mode ). when modrst gets asserted, an internal rese t occurs. the sim actively pulls down the rst pin for all internal reset sources. porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles $fffe $ffff 32 cycles system integration module (sim) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 228 freescale semiconductor 15.4 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the inter nal bus clocks. the sim counter also serves as a prescaler for the computer operating properly (cop) module. the sim counter overflow supplies the clock for the cop module. the si m counter is 12 bits long. 15.4.1 sim counter du ring power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initializ ed, it enables the clock generation module (cgm) to drive the bus clock state machine. 15.4.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the config1 register. if the ssrec bit is a 1, then the stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32 cgmxclk cycles. this is ideal for applications using crystals with the osceninstop bit set. external crystal applications should use the full stop recovery time, ssrec cleared, with the osceninstop bit cleared. see 5.2 functional description . 15.4.3 sim counter and reset states external reset has no effect on the sim counter. see 15.6.2 stop mode for details. the sim counter is free-running after all reset states. see 15.3.2 active resets from internal sources for counter control and internal reset recovery sequences. 15.5 exception control normal, sequential program execution can be changed in three different ways: ? interrupts: ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) ? reset ? break interrupts 15.5.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 15-8 shows interrupt entry timing. figure 15-9 shows interrupt recovery timing. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared). see figure 15-10 . exception control mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 229 figure 15-8 . interrupt entry timing figure 15-9. interrupt recovery timing 15.5.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 15-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1 [7:0] pc ? 1 [15:8] opcode operand i bit system integration module (sim) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 230 freescale semiconductor figure 15-10. interrupt processing no no no yes no no yes no yes yes from reset i bit set? irq interrupt cgm interrupt fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes yes i bit set? yes other interrupts no swi instruction rti instruction ? ? ? ? ? break interrupt ? exception control mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 231 figure 15-11 . interrupt recognition example 15.5.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 15.5.1.3 interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. table 15-3 summarizes the interrupt sources, hardware flag bits, hardware interrupt mask bits, interrupt status register flags, interrupt priority, and exception vectors. the interrupt status registers can be useful for debugging. interrupt status register 1 if6?if1 ? interrupt flags 1?6 these flags indicate the presence of interrupt requests from the sources shown in table 15-3 . 1 = interrupt request present 0 = no interrupt request present bit 0 and bit 1 ? always read 0 address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 15-12. interrupt status register 1 (int1) cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine system integration module (sim) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 232 freescale semiconductor table 15-3. interrupt sources source flag mask (1) 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. int register flag priority (2) 2. 0 = highest priority vector address reset none none none 0 $fffe ? $ffff swi instruction none none none 0 $fffc ? $fffd irq pin irqf imask1 if1 1 $fffa ? $fffb cgm change in lock pllf pllie if2 2 $fff8?$fff9 tim1 channel 0 ch0f ch0ie if3 3 $fff6?$fff7 tim1 channel 1 ch1f ch1ie if4 4 $fff4?$fff5 tim1 overflow tof toie if5 5 $fff2?$fff3 tim2 channel 0 ch0f ch0ie if6 6 $fff0?$fff1 tim2 channel 1 ch1f ch1ie if7 7 $ffee?$ffef tim2 overflow tof toie if8 8 $ffec?$ffed spi receiver full sprf sprie if9 9 $ffea?$ffeb spi overflow ovrf errie spi mode fault modf errie spi transmitter empty spt e sptie if10 10 $ffe8?$ffe9 sci receiver overrun or orie if11 11 $ffe6?$ffe7 sci noise flag nf neie sci framing error fe feie sci parity error pe peie sci receiver full scrf scrie if12 12 $ffe4?$ffe5 sci input idle idle ilie sci transmitter empty scte sctie if13 13 $ffe2?$ffe3 sci transmission complete tc tcie keyboard pin keyf imaskk if14 14 $ffe0?$ffe1 adc conversion complete coco aien if15 15 $ffde?$ffdf timebase tbif tbie if16 16 $ffdc?$ffdd mscan08 receiver wakeup wupif wupie if17 17 $ffda?$ffdb mscan08 error rwrnif twrnif rerif terrif boffif ovrif rwrnie twrnie rerrie terrie boffie ovrie if18 18 $ffd8?$ffd9 mscan08 receiver rxf rxfie if19 19 $ffd6?$ffd7 mscan08 transmitter txe2 txe1 txe0 txeie2 txeie1 txeie0 if20 20 $ffd4?$ffd5 tim2 channel 2 ch2f ch2ie if21 21 $ffd2?ffd3 tim2 channel 3 ch3f ch3ie if22 22 $ffd0?ffd1 tim2 channel 4 ch4f ch4ie if23 23 $ffce?ffcf tim2 channel 5 ch5f ch5ie if24 24 $ffcc?ffcd exception control mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 233 interrupt status register 2 if14?if7 ? interrupt flags 14?7 these flags indicate the presence of interrupt requests from the sources shown in table 15-3 . 1 = interrupt request present 0 = no interrupt request present interrupt status register 3 if22?if15 ? interrupt flags 22?15 these flags indicate the presence of an interrupt request from the source shown in table 15-3 . 1 = interrupt request present 0 = no interrupt request present interrupt status register 4 bits 7?2 ? always read 0 if24?if23 ? interrupt flags 24?23 these flags indicate the presence of an interrupt request from the source shown in table 15-3 . 1 = interrupt request present 0 = no interrupt request present address: $fe05 bit 7654321bit 0 read: if14 if13 if12 i f11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 r= reserved figure 15-13. interrupt status register 2 (int2) address: $fe06 bit 7654321bit 0 read: if22 if21 if20 if1 9if18if17if16if15 write:rrrrrrrr reset:00000000 r= reserved figure 15-14. interrupt status register 3 (int3) address: $fe07 bit 7654321bit 0 read:000000if24if23 write:rrrrrrrr reset:00000000 r= reserved figure 15-15. interrupt status register 4 (int4) system integration module (sim) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 234 freescale semiconductor 15.5.2 reset all reset sources always have equal and highest priority and cannot be arbitrated. 15.5.3 break interrupts the break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output (see chapter 18 timer interface module (tim1) and chapter 19 timer interface module (tim2) ). the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 15.5.4 status flag pr otection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from bei ng cleared by properly initializing the break clear flag enable bit (bcfe) in the sim break flag control register (bfcr). protecting flags in break mode ensures that set fl ags will not be cleared while in break mode. this protection allows registers to be freely read and writ ten during break mode without losing status flag information. setting the bcfe bit enables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status fl ags with a 2-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 15.6 low-power modes executing the wait or stop instruction puts the mcu in a low power-consumption mode for standby situations. the sim holds the cpu in a non-clocked st ate. the operation of each of these modes is described in the following subsections. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 15.6.1 wait mode in wait mode, the cpu clocks are inactive while the peripheral clocks continue to run. figure 15-16 shows the timing for wait mode entry. figure 15-16. wait mode entry timing wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. low-power modes mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 235 a module that is active during wait mode can wakeup the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wa it instruction during which the interrupt occurred. in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode also can be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (bsr). if the cop disable bit, copd, in the config1 register is 0, then the computer operat ing properly module (cop) is enabled and remains active in wait mode. figure 15-17 and figure 15-18 show the timing for wait recovery. figure 15-17. wait recovery from interrupt or break figure 15-18. wait recovery from internal reset 15.6.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset also caus es an exit from stop mode. the sim disables the clock generator module outputs (cgmout and cgmxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is sele ctable using the ssrec bit in config1. if ssrec is set, stop recovery is reduced from the normal dela y of 4096 cgmxclk cycles down to 32. this is ideal for applications using canned oscillators that do not require long startup times from stop mode. note external crystal applications should use the full stop recovery time by clearing the ssrec bit unless osceninstop bit is set in config2. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitsto pwait = rst pin, cpu interrupt, or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles system integration module (sim) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 236 freescale semiconductor the sim counter is held in reset from the executi on of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 15-19 shows stop mode entry timing. figure 15-20 shows stop mode recovery time from interrupt. note to minimize stop current, all pins conf igured as inputs should be driven to a 1 or 0. figure 15-19. stop mode entry timing figure 15-20. stop mode recovery from interrupt 15.7 sim registers the sim has three memory-mapped registers. table 15-4 shows the mapping of these registers. table 15-4. sim registers address register access mode $fe00 bsr user $fe01 srsr user $fe03 bfcr user stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. cgmxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period sim registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 237 15.7.1 break status register the break status register (bsr) contains a flag to i ndicate that a break caused an exit from wait mode. this register is only used in emulation mode. sbsw ? sim break stop/wait sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. 1 = wait mode was exited by break interrupt. 0 = wait mode was not exited by break interrupt. 15.7.2 sim reset status register this register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared. clear the sim reset status register by reading it. a power-on reset sets the por bit and clears all other bits in the register. the register is initialized on power up with the por bi t set and all other bits cl eared. during a por or any other internal reset, the rst pin is pulled low. after the pin is released, it will be sampled 32 cgmxclk cycles later. if the pin is not above v ih at this time, then the pin bit ma y be set, in addition to whatever other bits are set. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset:00000000 r = reserved 1. writing a 0 clears sbsw. figure 15-21. break status register (bsr) address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad modrst lvi 0 write: reset:10000000 = unimplemented figure 15-22. sim reset status register (srsr) system integration module (sim) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 238 freescale semiconductor ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr modrst ? monitor mode entry module reset bit 1 = last reset caused by monitor mode entry when vector locations $fffe and $ffff are $ff after por while irq = v dd 0 = por or read of srsr lvi ? low-voltage inhibit reset bit 1 = last reset caused by the lvi circuit 0 = por or read of srsr 15.7.3 break flag control register the break flag control register contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 15-23. break flag control register (bfcr) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 239 chapter 16 serial peripheral interface (spi) module 16.1 introduction this section describes the serial peripheral interfac e (spi) module, which allows full-duplex, synchronous, serial communications with peripheral devices. the text that follows describes t he spi. the spi i/o pin names are ss (slave select), spsck (spi serial clock), mosi (master out slave in), and miso (master in/s lave out). the spi shares four i/o pins with four parallel i/o ports. 16.2 features features of the spi module include: ? full-duplex operation ? master and slave modes ? double-buffered operation with separate transmit and receive registers ? four master mode frequencies (maximum = bus frequency 2) ? maximum slave mode frequency = bus frequency ? serial clock with programmable polarity and phase ? two separately enabled interrupts: ? sprf (spi receiver full) ? spte (spi transmitter empty) ? mode fault error flag with cpu interrupt capability ? overflow error flag with cpu interrupt capability ? programmable wired-or mode ? i/o (input/output) port bit(s) software configurabl e with pullup device(s) if configured as input port bit(s) 16.3 functional description the spi module allows full-dupl ex, synchronous, serial communica tion between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt driven. if a port bit is configured for input, then an inter nal pullup device may be enabled for that port bit. the following paragraphs describe the ope ration of the spi module. refer to figure 16-3 for a summary of the spi i/o registers. serial peripheral in terface (spi) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 240 freescale semiconductor figure 16-1. block diagram highlighting spi block and pins single breakpoint break module system integration module programmable timebase module monitor mode entry serial peripheral 6-channel timer interface module dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash ? 62,078 bytes user ram ? 2048 bytes monitor rom user flash vector space ? 52 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 rst (1) irq (1) interface module interrupt module computer operating properly module pta7/kbd7/ad15? 10-bit analog-to-digital converter module ptc6 (2) ptc5 (2) ptc4 (2, 3) ptc3 (2, 3) ptc2 (2, 3) ptc1/can rx (2, 3) ptc0/can tx (2, 3) ptd7/t2ch1 (2) ptd6/t2ch0 (2) ptd5/t1ch1 (2) ptd4/t1ch0 (2) ptd3/spsck (2) ptd2/mosi (2) ptd1/miso (2) ptd0/ss /mclk (2) pte1/rxd pte0/txd 2-channel timer interface module enhanced serial interface module security module power-on reset module memory map module configuration register 1?2 module power v ss v dd v ssa v dda 1. pin contains in tegrated pullup device. 2. ports are software configurable with pullup device if input port or pullup/pulldown device for keyboard input. 3. higher current drive port pins v ddad /v refh v ssad /v refl pte5?pte2 communications clock generator module cgmxfc phase locked loop 1?8 mhz oscillator portb ddrb ptb7/ad7? portf ddrf ptf7/t2ch5 module portg ddrg ptg7/ad23? ptf6/t2ch4 ptf5/t2ch3 ptf4/t2ch2 ptf3?pft0 (3) mscan module pta0/kbd0/ad8 (2) ptb0/ad0 ptg0/ad16 functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 241 figure 16-2. spi module block diagram addr.register name bit 7654321bit 0 $0010 spi control register (spcr) see page 255. read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $0011 spi status and control register (spscr) see page 256. read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 $0012 spi data register (spdr) see page 258. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset r = reserved = unimplemented figure 16-3. spi i/o register summary transmitter cpu interrupt request receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 busclk clock select 2 clock divider 8 32 128 clock logic cpha cpol spi sprie spe spwom sprf spte ovrf m s pin control logic receive data register sptie spe internal bus modfen errie control modf spmstr mosi miso spsck ss serial peripheral in terface (spi) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 242 freescale semiconductor 16.3.1 master mode the spi operates in master mode when the spi master bit, spmstr, is set. note in a multi-spi system, configure the spi modules as master or slave before enabling them. enable the master spi before enabling the slave spi. disable the slave spi before disabling the master spi. see 16.12.1 spi control register . only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the transmit data register. if the sh ift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte. the byte begins shifting out on the mosi pin under the control of the serial clock. see figure 16-4 . figure 16-4. full-duplex master-slave connections the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register. (see 16.12.2 spi status and control register .) through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. as the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the master?s miso pin. the transmission ends when the receiver full bit, sprf, becomes set. at the same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. writing to the spi data register (spdr) clears spte. 16.3.2 slave mode the spi operates in slave mode when spmstr is clear . in slave mode, the spsck pin is the input for the serial clock from the master mcu. before a data transmission occurs, the ss pin of the slave spi must be low. ss must remain low until the transmission is complete. see 16.6.2 mode fault error . in a slave spi module, data enters the shift register und er the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it transfers to the receive data register, and the sprf bit is set. to prevent an overflow condit ion, slave software then must read the receive data register before another full byte enters the shift register. shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss transmission formats mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 243 the maximum frequency of the spsck fo r an spi configured as a slave is the bus clock speed (which is twice as fast as the fastest master spsck clock t hat can be generated). th e frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. the slave must write to its tr ansmit data register at l east one bus cycle before the master starts the next transmission. otherwise, the byte already in the slave shift register shifts out on the miso pin. data written to the slave shift register during a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first e dge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. see 16.4 transmission formats . note spsck must be in the proper idle state before the slave is enabled to prevent spsck from appearing as a clock edge. 16.4 transmission formats during an spi transmission, data is simultaneously tr ansmitted (shifted out serially) and received (shifted in serially). a serial clock synchronizes shifting and sampling on the two serial data lines. a slave select line allows selection of an individual slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the slave select line can optionally be used to indicate multiple-master bus contention. 16.4.1 clock phase and polarity controls software can select any of four combinations of se rial clock (spsck) phase a nd polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no signi ficant effect on the transmission format. the clock phase (cpha) control bit selects one of tw o fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with periphera l slaves having different requirements. note before writing to the cpol bit or the cpha bit, disable the spi by clearing the spi enable bit (spe). 16.4.2 transmission format when cpha = 0 figure 16-5 shows an spi transmission in which cpha = 0. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slav e timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are di rectly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select serial peripheral in terface (spi) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 244 freescale semiconductor input (ss ) is low, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see 16.6.2 mode fault error .) when cpha = 0, the first spsck edge is the msb capture strobe. therefore, the slave must begin driving its data before the first spsck edge, and a falling edge on the ss pin is used to start the slave data transmission. the slave?s ss pin must be toggled back to high and then low again between each byte tr ansmitted as shown in figure 16-6 . when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the falling edge of ss . any data written after the falling edge is stored in th e transmit data register and transferred to the shift register after the current transmission. figure 16-5. transmission format (cpha = 0) figure 16-6. cpha/ss timing 16.4.3 transmission format when cpha = 1 figure 16-7 shows an spi transmission in which cpha = 1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slav e. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is low, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss ; to slave capture strobe byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1 transmission formats mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 245 pin of the master must be high or must be reconf igured as general-purpose i/o not affecting the spi. (see 16.6.2 mode fault error .) when cpha = 1, the master begins driving its mosi pin on the first spsck edge. therefore, the slave uses the first sps ck edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be preferable in systems having only one master and only one slave driving the miso data line. figure 16-7. transmission format (cpha = 1) when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the first edge of spsck. any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission. 16.4.4 transmission initiation latency when the spi is configured as a master (spmstr = 1), writing to the spdr st arts a transmission. cpha has no effect on the delay to the start of the transmiss ion, but it does affect the initial state of the spsck signal. when cpha = 0, the spsck signal remains inactive for the first half of the first spsck cycle. when cpha = 1, the first spsck cycl e begins with an edge on the spsck line from its inactive to its active level. the spi clock rate (selected by spr1 :spr0) affects the delay from the write to spdr and the start of the spi transmission. (see figure 16-8 .) the internal spi clock in the master is a free-running derivative of the internal mcu clock. to conserve power, it is enabled only when both the spe and spmstr bits are set. since the spi clock is free-runni ng, it is uncertain where the write to the spdr occurs relative to the slower spsck. this uncertainty causes the variation in the initiation delay shown in figure 16-8 . this delay is no longer than a single spi bi t time. that is, the maximum delay is two mcu bus cycles for div2, eight mcu bus cycles for di v8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss ; to slave capture strobe serial peripheral in terface (spi) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 246 freescale semiconductor figure 16-8. transmission start delay (master) write to spdr initiation delay bus mosi spsck cpha = 1 spsck cpha = 0 spsck cycle number msb bit 6 12 clock write to spdr earliest latest spsck = bus clock 2; earliest latest 2 possible start points spsck = bus clock 8; 8 possible start points earliest latest spsck = bus clock 32; 32 possible start points earliest latest spsck = bus clock 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock initiation delay from write spdr to transfer begin queuing transm ission data mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 247 16.5 queuing tr ansmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transm itted immediately after the previous transmission has completed. the spi transmitter empty flag (spte) indicates when the transmit data buffer is ready to accept new data. write to the transmit data register only when spte is high. figure 16-9 shows the timing associated with doing back-to-back transmiss ions with the spi (spsck has cpha: cpol = 1:0). figure 16-9. sprf/spte cpu interrupt timing the transmit data buffer allows back- to-back transmissions without the sl ave precisely timing its writes between transmissions as in a system with a single data buffer. also, if no new data is written to the data buffer, the last value contained in the shift r egister is the next data word to be transmitted. for an idle master or idle slave that has no data loaded into its transmit buffer, the spte is set again no more than two bus cycles after the transmit buffer emptie s into the shift register. this allows the user to queue up a 16-bit value to send. for an already active sl ave, the load of the shift register cannot occur until the transmission is completed. this implies that a back-to-back write to the transmit data register is not possible. spte indicates when the next write can occur. bit 3 mosi spsck spte write to spdr 1 cpu writes byte 2 to spdr, queueing byte 2 cpu writes byte 1 to spdr, clearing spte bit. byte 1 transfers from transmit data 3 1 2 2 3 5 register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set. cpha:cpol = 1:0 serial peripheral in terface (spi) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 248 freescale semiconductor 16.6 error conditions the following flags signal spi error conditions: ? overflow (ovrf) ? failing to read the spi data register before the next full byte enters the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read. ovrf is in the spi status and control register. ? mode fault error (modf) ? the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. modf is in the spi status and control register. 16.6.1 overflow error the overflow flag (ovrf) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of th e next transmission occurs. the bit 1 capture strobe occurs in the middle of spsck cycle 7 (see figure 16-5 and figure 16-7 .) if an overflow occurs, all data received after the overflow and before the ovrf bit is cleared does not transfer to the receive data register and does not set the spi receiver full bit (sprf). the unread data that transferred to the receive data register before the overflow occurred can still be read. therefore, an overflow error always indicates the loss of data. clear the overflow flag by reading the spi status and control register and then reading the spi data register. ovrf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector (see figure 16-12 .) it is not possible to enable modf or ovrf individually to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. if the cpu sprf interrupt is enabled and the ovrf in terrupt is not, watch for an overflow condition. figure 16-10 shows how it is possible to miss an overflow. the first part of figure 16-10 shows how it is possible to read the spscr and spdr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf bit c an be set in between the time that spscr and spdr are read. figure 16-10. missed read of overflow condition read read ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is not cleared. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. spscr spdr error conditions mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 249 in this case, an overflow can be missed easily. since no more sprf interrupts can be generated until this ovrf is serviced, it is not obvious that bytes are being lost as more transmissions are completed. to prevent this, either enable the ovrf interrupt or do another read of the spscr following the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions can set the sprf bit. figure 16-11 illustrates this process. g enerally, to avoid this second spscr read, enable the ovrf to the cpu by setting the errie bit. figure 16-11. clearing sprf when ovrf interrupt is not enabled 16.6.2 mode fault error setting spmstr selects master mode and configures the spsck and mosi pins as outputs and the miso pin as an input. clearing spmstr selects sl ave mode and configures the spsck and mosi pins as inputs and the miso pin as an output. the mode fault bit, modf, becomes set any time the state of the slave select pin, ss , is inconsistent with the mode selected by spmstr. to prevent spi pin contention and damage to the mcu, a mode fault error occurs if: ?the ss pin of a slave spi goes high during a transmission ?the ss pin of a master spi goes low at any time for the modf flag to be set, the mode fault error enable bit (modfen) must be set. clearing the modfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. modf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. (see figure 16-12 .) it is not possible to enable modf or ovrf individual ly to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. read read ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. spscr spdr serial peripheral in terface (spi) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 250 freescale semiconductor in a master spi with the mode fault enable bit (modfe n) set, the mode fault flag (modf) is set if ss goes low. a mode fault in a master spi causes the following events to occur: ? if errie = 1, the spi generates an spi receiver/error cpu interrupt request. ? the spe bit is cleared. ? the spte bit is set. ? the spi state counter is cleared. ? the data direction register of the shared i/o port regains control of port drivers. note to prevent bus contention with another master spi after a mode fault error, clear all spi bits of the data direction register of the shared i/o port before enabling the spi. when configured as a slave (spmstr = 0), the modf flag is set if ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends once the incoming spsck goes back to its idle level following the shift of the eighth data bit. when cpha = 1, the transmission begins when the spsck leaves its idle level and ss is already low. the transmi ssion continues until the spsck returns to its idle level following the shift of the last data bit. see 16.4 transmission formats . note setting the modf flag does not clear the spmstr bit. spmstr has no function when spe = 0. reading spmstr when modf = 1 shows the difference between a modf occurring when the spi is a master and when it is a slave. when cpha = 0, a modf occurs if a slave is selected (ss is low) and later unselected (ss is high) even if no spsck is sent to that slave. this happens because ss low indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later unselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), modf generates an spi re ceiver/error cpu interrupt request if the errie bit is set. the modf bit does not clear the spe bit or re set the spi in any way. software can abort the spi transmission by clearing the spe bit of the slave. note a high on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. to clear the modf flag, read the spscr with the modf bit set and then write to the spcr register. this entire clearing mechanism must occur with no modf condition existing or else the flag is not cleared. interrupts mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 251 16.7 interrupts four spi status flags can be enabled to generate cpu interrupt requests. see table 16-1 . reading the spi status and control register with sprf set and then reading the receive data register clears sprf. the clearing mechanism for the spte flag is always just a write to the transmit data register. the spi transmitter interrupt enable bit (sptie) enables the spte flag to generate transmitter cpu interrupt requests, provided that the spi is enabled (spe = 1). the spi receiver interrupt enable bit (sprie) enables sprf to generate receiver cpu interrupt requests, regardless of the state of spe. see figure 16-12 . figure 16-12. spi interrupt request generation the error interrupt enable bit (errie) enables both the modf and ovrf bits to generate a receiver/error cpu interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf bit is enabled by the errie bit to generate receiver/error cpu interrupt requests. table 16-1. spi interrupts flag request spte transmitter empty spi transmitter cpu interrupt request (sptie = 1, spe = 1) sprf receiver full spi receiver cpu interrupt request (sprie = 1) ovrf overflow spi receiver/error interrupt request (errie = 1) modf mode fault spi receiver/error interrupt request (errie = 1) spte sptie sprf sprie spe cpu interrupt request cpu interrupt request spi transmitter spi receiver/error errie modf ovrf serial peripheral in terface (spi) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 252 freescale semiconductor the following sources in the spi status and control register can generate cpu interrupt requests: ? spi receiver full bit (sprf) ? sprf becomes set ever y time a byte transfers from the shift register to the receive data register. if the spi receiver interrupt enable bit, sprie, is also set, sprf generates an spi receiver/error cpu interrupt request. ? spi transmitter empty (spte) ? spte becomes set every time a byte transfers from the transmit data register to the shift register. if the spi transmit interrupt enable bit, sptie, is also set, spte generates an spte cpu interrupt request. 16.8 resetting the spi any system reset completely resets the spi. partial resets occur whenever the spi enable bit (spe) is 0. whenever spe is 0, the following occurs: ? the spte flag is set. ? any transmission currently in progress is aborted. ? the shift register is cleared. ? the spi state counter is cleared, making it ready for a new complete transmission. ? all the spi port logic is defaul ted back to being general-purpose i/o. these items are reset only by a system reset: ? all control bits in the spcr register ? all control bits in the spscr regist er (modfen, errie, spr1, and spr0) ? the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe betw een transmissions without having to set all control bits again when spe is set back high for t he next transmission. by not resetting the sprf, ovrf, and modf flags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing 0 to the spe bit. the spi can also be disabled by a mode fault occurring in an spi that wa s configured as a master with the modfen bit set. 16.9 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 16.9.1 wait mode the spi module remains active after the execution of a wait instruction. in wait mode the spi module registers are not accessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. to exit wait mode when an overflow condition occu rs, enable the ovrf bit to generate cpu interrupt requests by setting the error interrupt enable bit (errie). see 16.7 interrupts . spi during break interrupts mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 253 16.9.2 stop mode the spi module is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions. spi operation resumes after an external interrupt. if stop mode is exited by reset, any transfer in progress is aborted, and the spi is reset. 16.10 spi during break interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. bcfe in the sim break flag control r egister (sbfcr) enables software to clear status bits during the break state. see chapter 15 system integration module (sim). to allow software to clear status bits during a break interrupt, write a 1 to bcfe. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to bcfe. with bcfe at 0 (its default state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bc fe is 0. after the break, doing the second step clears the status bit. since the spte bit cannot be cleared during a break wi th bcfe cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register. therefore, a write to the spdr in break mode with bcfe cleared has no effect. 16.11 i/o signals the spi module has four i/o pins: ? miso ? master input/slave output ? mosi ? master output/slave input ? spsck ? serial clock ?ss ? slave select 16.11.1 miso (mas ter in/slave out) miso is one of the two spi module pins that transmits se rial data. in full duplex operation, the miso pin of the master spi module is connected to the miso pin of the slave spi module. the master spi simultaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enabled only w hen the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is 0 and its ss pin is low. to support a multiple-slave system, a high on the ss pin puts the miso pin in a high-impedance state. when enabled, the spi controls data direction of the mi so pin regardless of the st ate of the data direction register of the shared i/o port. 16.11.2 mosi (master out/slave in) mosi is one of the two spi module pins that transmits serial data. in full-duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. serial peripheral in terface (spi) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 254 freescale semiconductor when enabled, the spi controls data direction of the mo si pin regardless of the st ate of the data direction register of the shared i/o port. 16.11.3 spsck (serial clock) the serial clock synchronizes data transmission between master and sl ave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the cl ock input. in full-duplex operation, the master and slave mcus exchange a byte of data in eight serial clock cycles. when enabled, the spi contro ls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port. 16.11.4 ss (slave select) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. (see 16.4 transmission formats .) since it is used to indicate the start of a transmission, ss must be toggled high and low between each byte transmitted for the cpha = 0 format. however, it can remain low between transmissions for the cpha = 1 format. see figure 16-13 . when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of ss from creating a modf error. see 16.12.2 spi status and control register. figure 16-13. cpha/ss timing note a high on the ss pin of a slave spi puts the miso pin in a high-impedance state. the slave spi ignores all inco ming spsck clocks, even if it was already in the middle of a transmission. when an spi is configured as a master, the ss input can be used in conjunc tion with the modf flag to prevent multiple masters from driving mosi and spsck. (see 16.6.2 mode fault error.) for the state of the ss pin to set the modf flag, the modfen bit in t he spsck register must be set. if modfen is 0 for an spi master, the ss pin can be used as a general-purpose i/o under the control of the data direction register of the shared i/o port. when modfen is 1, ss is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and reading the port data register. see table 16-2. byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1 i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 255 16.12 i/o registers three registers control and monitor spi operation: ? spi control register (spcr) ? spi status and control register (spscr) ? spi data register (spdr) 16.12.1 spi control register the spi control register: ? enables spi module interrupt requests ? configures the spi module as master or slave ? selects serial clock polarity and phase ? configures the spsck, mosi, and miso pins as open-drain outputs ? enables the spi module sprie ? spi receiver interrupt enable bit this read/write bit enables cpu interrupt requests generated by the sprf bit. the sprf bit is set when a byte transfers from the sh ift register to the receive data register. reset clears the sprie bit. 1 = sprf cpu interrupt requests enabled 0 = sprf cpu interrupt requests disabled spmstr ? spi master bit this read/write bit selects master mode operation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode table 16-2. spi configuration spe spmstr modfen spi configuration function of ss pin 0 x (1)) 1. x = don?t care x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi address: $0010 bit 7654321bit 0 read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 r = reserved figure 16-14. spi control register (spcr) serial peripheral in terface (spi) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 256 freescale semiconductor cpol ? clock polarity bit this read/write bit determines the logic stat e of the spsck pin betw een transmissions. (see figure 16-5 and figure 16-7 .) to transmit data between spi modules, the spi modules must have identical cpol values. reset cl ears the cpol bit. cpha ? clock phase bit this read/write bit controls the timing relati onship between the serial clock and spi data. (see figure 16-5 and figure 16-7 .) to transmit data between spi modules, the spi modules must have identical cpha values. when cpha = 0, the ss pin of the slave spi module must be high between bytes. (see figure 16-13 .) reset sets the cpha bit. spwom ? spi wired-or mode bit this read/write bit disables the pullup devices on pins spsck, mos i, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull spsc k, mosi, and miso pins spe ? spi enable this read/write bit enables the spi module. cleari ng spe causes a partial reset of the spi. (see 16.8 resetting the spi .) reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie? spi transmit interrupt enable this read/write bit enables cpu interrupt requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. reset clears the sptie bit. 1 = spte cpu interrupt requests enabled 0 = spte cpu interrupt requests disabled 16.12.2 spi status and control register the spi status and control register c ontains flags to si gnal these conditions: ? receive data register full ? failure to clear sprf bit before next byte is received (overflow error) ? inconsistent logic level on ss pin (mode fault error) ? transmit data register empty the spi status and control register also c ontains bits that perform these functions: ? enable error interrupts ? enable mode fault error detection ? select master spi baud rate address: $0011 bit 7654321bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 = unimplemented figure 16-15. spi status and control register (spscr) i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 257 sprf ? spi receiver full bit this clearable, read-only flag is set each time a byte tr ansfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the sprie bit in the spi control register is set also. during an sprf cpu interrupt, the cpu clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. reset clears the sprf bit. 1 = receive data register full 0 = receive data register not full errie ? error interrupt enable bit this read/write bit enables the modf and ovrf bits to generate cpu interrupt requests. reset clears the errie bit. 1 = modf and ovrf can generate cpu interrupt requests 0 = modf and ovrf cannot generate cpu interrupt requests ovrf ? overflow bit this clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. in an ov erflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the receive data register. reset clears the ovrf bit. 1 = overflow 0 = no overflow modf ? mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission with modfen set. in a master spi, the modf flag is set if the ss pin goes low at any time with the modfen bit set. clear modf by reading the spi stat us and control register (spscr) with modf set and then writing to the spi control regi ster (spcr). reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte ? spi transmitter empty bit this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an spte cpu interrupt request if sptie in the spi control register is set also. note do not write to the spi data register unless spte is high. during an spte cpu interrupt, the cpu clears spt e by writing to the transmit data register. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data register not empty modfen ? mode fault enable bit this read/write bit, when set, allows the modf flag to be set. if the modf flag is set, clearing modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is 0, then the ss pin is available as a general-purpose i/o. serial peripheral in terface (spi) module mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 258 freescale semiconductor if the modfen bit is 1, then the ss pin is not available as a general-purpose i/o. when the spi is enabled as a slave, the ss pin is not available as a general-pu rpose i/o regardless of the value of modfen. see 16.11.4 ss (slave select). if the modfen bit is 0, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. see 16.6.2 mode fault error. spr1 and spr0 ? spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 16-3 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use this formula to calculate the spi baud rate: 16.12.3 spi data register the spi data register consists of the read-only receive data register and the write-only transmit data register. writing to the spi data register writes dat a into the transmit data register. reading the spi data register reads data from the receive data register. the transmit data and receive data registers are separate registers that can c ontain different values. see figure 16-2 . r7?r0/t7?t0 ? receive/transmit data bits note do not use read-modify-write instructio ns on the spi data register since the register read is not the same as the register written. table 16-3. spi master baud rate selection spr1 and spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 address: $0012 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 16-16. spi data register (spdr) baud rate = busclk bd mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 259 chapter 17 timebase module (tbm) 17.1 introduction this section describes the timebase module (tbm). the tbm will generate periodic interrupts at user selectable rates using a counter cloc ked by the external clock source. this tbm version uses 15 divider stages, eight of which are user selectable. a configur ation option bit to select an additional 128 divide of the external clock source can be selected. see chapter 5 configuration register (config) 17.2 features features of the tbm module include: ? external clock or an additional divide-by-128 sele cted by configuration option bit as clock source ? software configurable periodic interrupts with di vide-by: 8, 16, 32, 64, 128, 2048, 8192, and 32768 taps of the selected clock source ? configurable for operation during stop m ode to allow periodic wakeup from stop 17.3 functional description this module can generate a periodic interrupt by di viding the clock source supplied from the clock generator module, cgmxclk. the counter is initialized to all 0s when tbon bit is cleared. the counter, shown in figure 17-1 , starts counting when the tbon bit is set. when the counter ov erflows at the tap selected by tbr2?tbr0, the tbif bit gets set. if the tbie bit is set, an interrupt request is sent to the cpu. the tbif flag is cleared by writing a 1 to the tack bit. the first time the tbif flag is set after enabling the timebase module, the interrupt is generated at approximately half of the ov erflow period. subsequent events occur at the exact period. the timebase module may remain active after execution of the stop instruction if the crystal oscillator has been enabled to operate during stop mode through the osceninstop bit in the configuration register. the timebase module can be used in this mode to generate a periodic wakeup from stop mode. 17.4 interrupts the timebase module can periodically interrupt the cpu with a rate defined by the selected tbmclk and the select bits tbr2?tbr0. when the timebase counter c hain rolls over, the tbif flag is set. if the tbie bit is set, enabling the timebase interrupt, the c ounter chain overflow will generate a cpu interrupt request. note interrupts must be acknowledged by writing a 1 to the tack bit. timebase module (tbm) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 260 freescale semiconductor figure 17-1. timebase block diagram 17.5 tbm interrupt rate the interrupt rate is determined by the equation: where: f cgmxclk =frequency supplied from th e clock generator (cgm) module divider = divider value as determined by tbr2?tbr0 settings and tmbclksel, see table 17-1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 sel 0 0 0 0 0 1 0 1 0 0 1 1 tbif tbr1 tbr0 tbie tbmint tbon 2 r tack tbr2 1 0 0 1 0 1 1 1 0 1 1 1 tbmclk from cgm module tmbclksel from config2 divide by 128 prescaler 0 1 cgmxclk t tbmrate = divider f cgmxclk low-power modes mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 261 as an example, a 4.9152 mhz crys tal, with the tmbclksel set fo r divide-by-128 and the tbr2?tbr0 set to {011}, the divider is 16,384 and the interrupt rate calculates to: note do not change tbr2?tbr0 bits while the timebase is enabled (tbon = 1). 17.6 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 17.6.1 wait mode the timebase module remains active after execution of the wait instruction. in wait mode the timebase register is not accessible by the cpu. if the timebase functions are not required during wa it mode, reduce the power consumption by stopping the timebase before executing the wait instruction. 17.6.2 stop mode the timebase module may remain active after execution of the stop instruction if the oscillator has been enabled to operate during stop mode through the osceninstop bit in the configuration register. the timebase module can be used in this mode to generate a periodic wakeup from stop mode. if the oscillator has not been enabled to operate in stop mode, the timebase module will not be active during stop mode. in stop mode, the timebase r egister is not accessible by the cpu. if the timebase functions are not required during stop mode, reduce power consumption by disabling the timebase module before execut ing the stop instruction. table 17-1. timebase divider selection divider tbr2 tbr1 tbr0 tmbclksel 01 0 0 0 32,768 4,194,304 0 0 1 8192 1,048,576 0 1 0 2048 262144 0 1 1 128 16,384 1 0 0 64 8192 1 0 1 32 4096 1 1 0 16 2048 1 1 1 8 1024 16,384 4.9152 x 10 6 = 3.33 ms timebase module (tbm) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 262 freescale semiconductor 17.7 timebase control register the timebase has one register, the timebase control register (tbcr), which is used to enable the timebase interrupts and set the rate. tbif ? timebase interrupt flag this read-only flag bit is set when th e timebase counter has rolled over. 1 = timebase interrupt pending 0 = timebase interrupt not pending tbr2?tbr0 ? timebase divider selection bits these read/write bits select the tap in the counter to be used for timebase interrupts as shown in table 17-1 . note do not change tbr2?tbr0 bits while the timebase is enabled (tbon = 1). tack? timebase acknowledge bit the tack bit is a write-only bit and always reads as 0. writing a 1 to this bit clears tbif, the timebase interrupt flag bit. writing a 0 to this bit has no effect. 1 = clear timebase interrupt flag 0 = no effect tbie ? timebase interrupt enabled bit this read/write bit enables the timebase interrupt when the tbif bit becomes set. reset clears the tbie bit. 1 = timebase interrupt is enabled. 0 = timebase interrupt is disabled. tbon ? timebase enabled bit this read/write bit enables the timebase. timebase may be turned off to reduce power consumption when its function is not necessary. the counter can be initialized by clearing and then setting this bit. reset clears the tbon bit. 1 = timebase is enabled. 0 = timebase is disabled and t he counter initialized to 0s. address: $001c bit 7654321bit 0 read: tbif tbr2 tbr1 tbr0 0 tbie tbon r write: tack reset:00000000 = unimplemented r = reserved figure 17-2. timebase control register (tbcr) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 263 chapter 18 timer interface module (tim1) 18.1 introduction this section describes the timer interface module (tim1). tim1 is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width- modulation functions. figure 18-2 is a block diagram of the tim1. 18.2 features features of the tim1 include the following: ? two input capture/output compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action ? buffered and unbuffered pulse width modulation (pwm) signal generation ? programmable tim1 clock input with 7-fre quency internal bus clock prescaler selection ? free-running or modulo up-count operation ? toggle any channel pin on overflow ? tim1 counter stop and reset bits 18.3 functional description figure 18-2 shows the structure of the tim1. the central component of the tim1 is the 16-bit tim1 counter that can operate as a free-running counter or a modulo up-counter. the tim1 counter provides the timing reference for the input capture and out put compare functions. the tim1 counter modulo registers, t1modh:t1modl, control the modulo value of the tim1 counter. software can read the tim1 counter value at any time wit hout affecting the counting sequence. the two tim1 channels are programmable independentl y as input capture or output compare channels. 18.3.1 tim1 counter prescaler the tim1 clock source is one of the seven prescaler outputs. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim1 status and control register (t1sc) select the tim1 clock source. 18.3.2 input capture with the input capture function, the tim1 can capt ure the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the tim1 latches the contents of the tim1 counter into the tim1 channel registers, t1chx h:t1chxl. the polarity of the active edge is programmable. input captures can generate tim1 ce ntral processor unit (cpu) interrupt requests. timer interface module (tim1) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 264 freescale semiconductor figure 18-1. block diagram highlighting tim1 block and pins single breakpoint break module system integration module programmable timebase module monitor mode entry serial peripheral 6-channel timer interface module dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash ? 62,078 bytes user ram ? 2048 bytes monitor rom user flash vector space ? 52 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 rst (1) irq (1) interface module interrupt module computer operating properly module pta7/kbd7/ad15? 10-bit analog-to-digital converter module ptc6 (2) ptc5 (2) ptc4 (2, 3) ptc3 (2, 3) ptc2 (2, 3) ptc1/can rx (2, 3) ptc0/can tx (2, 3) ptd7/t2ch1 (2) ptd6/t2ch0 (2) ptd5/t1ch1 (2) ptd4/t1ch0 (2) ptd3/spsck (2) ptd2/mosi (2) ptd1/miso (2) ptd0/ss /mclk (2) pte1/rxd pte0/txd 2-channel timer interface module enhanced serial interface module security module power-on reset module memory map module configuration register 1?2 module power v ss v dd v ssa v dda 1. pin contains in tegrated pullup device. 2. ports are software configurable with pullup device if input port or pullup/pulldown device for keyboard input. 3. higher current drive port pins v ddad /v refh v ssad /v refl pte5?pte2 communications clock generator module cgmxfc phase locked loop 1?8 mhz oscillator portb ddrb ptb7/ad7? portf ddrf ptf7/t2ch5 module portg ddrg ptg7/ad23? ptf6/t2ch4 ptf5/t2ch3 ptf4/t2ch2 ptf3?pft0 (3) mscan module pta0/kbd0/ad8 (2) ptb0/ad0 ptg0/ad16 functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 265 figure 18-2. tim1 block diagram 18.3.3 output compare with the output compare function, the tim1 can gener ate a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim1 can set, clear, or toggle the channel pin. output compares can generate tim1 cpu interrupt requests. 18.3.3.1 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 18.3.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the tim1 channel registers. an unsynchronized write to the tim1 channel regist ers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim1 over flow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim1 may pass the new value before it is written. prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch t1ch0h:t1ch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch t1ch1h:t1ch1l channel 0 channel 1 t1modh:t1modl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus ms1a internal bus clock ptd5/t1ch1 ptd4/t1ch0 interrupt logic port logic interrupt logic interrupt logic port logic timer interface module (tim1) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 266 freescale semiconductor addr. register name bit 7654321bit 0 $0020 tim1 status and control register (t1sc) see page 271. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 tim1 counter register high (t1cnth) see page 273. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0022 tim1 counter register low (t1cntl) see page 273. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0023 tim1 counter modulo register high (t1modh) see page 273. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 $0024 tim1 counter modulo register low (t1modl) see page 273. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $0025 tim1 channel 0 status and control register (t1sc0) see page 274. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 tim1 channel 0 register high (t1ch0h) see page 277. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0027 tim1 channel 0 register low (t1ch0l) see page 277. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset $0028 tim1 channel 1 status and control register (t1sc1) see page 274. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 tim1 channel 1 register high (t1ch1h) see page 277. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $002a tim1 channel 1 register low (t1ch1l) see page 277. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset = unimplemented figure 18-3. tim1 i/o register summary functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 267 use the following methods to synchronize unbuffer ed changes in the output compare value on channel x: ? when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. ? when changing to a larger output compare value, enable tim1 overflow interrupts and write the new value in the tim1 overflow interrupt routine. the tim1 overflow interrupt occurs at the end of the current counter overflow period. writing a larg er value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 18.3.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the t1ch0 pin. the tim1 channel registers of the linked pair alternately control the output. setting the ms0b bit in tim1 channel 0 status and co ntrol register (tsc0) link s channel 0 and channel 1. the output compare value in the tim1 channel 0 registers initially controls the output on the t1ch0 pin. writing to the tim1 channel 1 registers enables the tim1 channel 1 registers to synchronously control the output after the tim1 overflows. at each subsequent overflow, the tim1 channel registers (0 or 1) that control the output are the ones written to last. t1sc0 controls and monitors the buffered output compare function, and tim1 channel 1 status and control regi ster (t1sc1) is unused. while the ms0b bit is set, the channel 1 pin, t1ch1, is available as a general-purpose i/o pin. note in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 18.3.4 pulse widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim1 can generate a pwm signal. the value in the tim1 counter modulo registers determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the tim1 counter modulo registers. the time between overflows is the period of the pwm signal. as figure 18-4 shows, the output compare value in the tim1 channel registers determines the pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim1 to clear the channel pin on output compare if the polarity of the pwm pulse is 1 (elsxa = 0). program the tim1 to set the pin if the polarity of the pwm pulse is 0 (elsxa = 1). the value in the tim1 counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim1 counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is 000. see 18.8.1 tim1 status and control register. the value in the tim1 channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim1 channel registers produces a duty cycle of 128/256 or 50%. timer interface module (tim1) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 268 freescale semiconductor figure 18-4. pwm period and pulse width 18.3.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 18.3.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tim1 channel registers. an unsynchronized write to the tim1 channel regi sters to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim1 overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim1 may pass the ne w value before it is written to the timer channel (t1chxh:t1chxl) registers. use the following methods to synchronize unbuffer ed changes in the pwm pulse width on channel x: ? when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. ? when changing to a longer pulse width, enable ti m1 overflow interrupts and write the new value in the tim1 overflow interrupt routine. the tim1 overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. tchx period pulse width overflow overflow overflow output compare output compare output compare tchx polarity = 1 (elsxa = 0) polarity = 0 (elsxa = 1) functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 269 18.3.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the t1ch0 pin. the tim1 channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim1 channel 0 status and cont rol register (t1sc0) links channel 0 and channel 1. the tim1 channel 0 registers initially control the pulse width on the t1ch0 pin. writing to the tim1 channel 1 registers enables the tim1 channel 1 regist ers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim1 channel registers (0 or 1) that control the pulse width are the ones written to la st. t1sc0 controls and monitors the buffered pwm function, and tim1 channel 1 status and control regi ster (t1sc1) is unused. while the ms0b bit is set, the channel 1 pin, t1ch1, is ava ilable as a general-purpose i/o pin. note in buffered pwm signal generation, do not write new pulse width values to the currently active channel regist ers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 18.3.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim1 status and control register (t1sc): a. stop the tim1 counter by setting the tim1 stop bit, tstop. b. reset the tim1 counter and prescaler by setting the tim1 reset bit, trst. 2. in the tim1 counter modulo registers (t1modh:t1modl), write the value for the required pwm period. 3. in the tim1 channel x registers (t1chxh:t1chxl) , write the value for the required pulse width. 4. in tim1 channel x status and control register (t1scx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode se lect bits, msxb:msxa. see table 18-2 . b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (polarity 1 ? to clear output on compare) or 1:1 (polarity 0 ? to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. see table 18-2 . note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim1 status control register (t1sc), clear the tim1 stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim1 channel 0 registers (tch0h:tch0l) initially contro l the buffered pwm output. tim1 status control timer interface module (tim1) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 270 freescale semiconductor register 0 (tscr0) controls and monitors the pwm si gnal from the linked channels. ms0b takes priority over ms0a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim1 overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. see 18.8.4 tim1 channel status and control registers . 18.4 interrupts the following tim1 sources can generate interrupt requests: ? tim1 overflow flag (tof) ? the tof bit is set when the tim1 counter reaches the modulo value programmed in the tim1 counter modulo registers. the tim1 overflow interrupt enable bit, toie, enables tim1 overflow cpu interrupt requests. to f and toie are in the tim1 status and control register. ? tim1 channel flags (ch1f:ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interr upt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie =1. chxf and chxie are in the tim1 channel x status and control register. 18.5 wait mode the wait instruction puts the mcu in low power-consumption standby mode. the tim1 remains active after the execution of a wait instruction. in wait mode the tim1 registers are not accessible by the cpu. any enabled cpu interrupt request from the tim1 can bring the mcu out of wait mode. if tim1 functions are not required during wait mode, reduce power consumption by stopping the tim1 before executing the wait instruction. 18.6 tim1 during break interrupts a break interrupt stops the tim1 counter and inhibits input captures. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see figure 15-21. break status register (bsr) . to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. input/output signals mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 271 18.7 input/output signals port d shares two of its pins with the tim1. the two tim1 channel i/o pins are ptd4/t1ch0 and ptd5/t1ch1. each channel i/o pin is programmable independently as an input capture pin or an output compare pin. ptd4/t1ch0 can be configured as a buffered output compare or buffered pwm pin. 18.8 input/output registers the following i/o registers control and monitor operation of the tim: ? tim1 status and control register (t1sc) ? tim1 counter registers (t1cnth:t1cntl) ? tim1 counter modulo registers (t1modh:t1modl) ? tim1 channel status and control registers (t1sc0 and t1sc1) ? tim1 channel registers (t1ch0h:t1ch0l and t1ch1h:t1ch1l) 18.8.1 tim1 status and control register the tim1 status and control register (t1sc) does the following: ? enables tim1 overflow interrupts ? flags tim1 overflows ? stops the tim1 counter ? resets the tim1 counter ? prescales the tim1 counter clock tof ? tim1 overflow flag bit this read/write flag is set when the tim1 counter reaches the modulo value programmed in the tim1 counter modulo registers. clear tof by reading the tim1 status and control register when tof is set and then writing a 0 to tof. if another tim1 overflow occurs before the clearing sequence is complete, then writing 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears th e tof bit. writing a 1 to tof has no effect. 1 = tim1 counter has reached modulo value 0 = tim1 counter has not reached modulo value toie ? tim1 overflow interrupt enable bit this read/write bit enables tim1 overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tim1 overflow interrupts enabled 0 = tim1 overflow interrupts disabled address: $0020 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 18-5. tim1 status and control register (t1sc) timer interface module (tim1) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 272 freescale semiconductor tstop ? tim1 stop bit this read/write bit stops the tim1 counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim1 counter until software clears the tstop bit. 1 = tim1 counter stopped 0 = tim1 counter active note do not set the tstop bit before entering wait mode if the tim1 is required to exit wait mode. also, when the tstop bit is set and the timer is configured for input capture operation, i nput captures are inhibited until the tstop bit is cleared. trst ? tim1 reset bit setting this write-only bit resets the tim1 counter a nd the tim1 prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim1 counter is reset and always reads as 0. reset clears the trst bit. 1 = prescaler and tim1 counter cleared 0 = no effect note setting the tstop and trst bits simultaneously stops the tim1 counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the tim1 counter as table 18-1 shows. reset clears the ps[2:0] bits. table 18-1. prescaler selection ps2 ps1 ps0 tim1 clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 1 1 1 not available input/output registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 273 18.8.2 tim1 counter registers the two read-only tim1 counter registers contain the high and low bytes of the value in the tim1 counter. reading the high byte (t1cnth) latches the contents of the low byte (t1cntl) into a buffer. subsequent reads of t1cnth do not affect the latched t1cntl value until t1cntl is read. reset clears the tim1 counter registers. setting the tim1 reset bit (trst) also clears the tim1 counter registers. note if you read t1cnth during a break interrupt, be sure to unlatch t1cntl by reading t1cntl before exiting the break interrupt. otherwise, t1cntl retains the value latched during the break. 18.8.3 tim1 counter modulo registers the read/write tim1 modulo registers contain the modulo value for the tim1 counter. when the tim1 counter reaches the modulo value, the overflow fl ag (tof) becomes set, and the tim1 counter resumes counting from $0000 at the next timer clock. writing to the high byte (t1modh) inhibits the tof bit and overflow interrupts until the low byte (t1modl) is wr itten. reset sets the tim1 counter modulo registers. note reset the tim1 counter before writing to the tim1 counter modulo registers. address: $0021 t1cnth bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $0022 t1cntl bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 18-6. tim1 counter registers (t1cnth:t1cntl) address: $0023 t1modh bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 address: $0024 t1modl bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 figure 18-7. tim1 counter modulo registers (t1modh:t1modl) timer interface module (tim1) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 274 freescale semiconductor 18.8.4 tim1 channel status and control registers each of the tim1 channel status and control registers does the following: ? flags input captures and output compares ? enables input capture and output compare interrupts ? selects input capture, output compare, or pwm operation ? selects high, low, or toggling output on output compare ? selects rising edge, falling edge, or any edge as the active input capture trigger ? selects output toggling on tim1 overflow ? selects 0% and 100% pwm duty cycle ? selects buffered or unbuffered output compare/pwm operation chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the tim1 counter registers matches the value in the tim1 channel x registers. clear chxf by reading the tim1 channel x status and control register with chxf set and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tim1 cpu interrupt service requests on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled address: $0025 t1sc0 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 address: $0028 t1sc1 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 18-8. tim1 channel status and control registers (t1sc0:t1sc1) input/output registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 275 msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim1 channel 0 status and control register. setting ms0b disables the channel 1 status and control register and reverts t1ch1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 18-2 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin (see table 18-2 ). reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim1 status and control register (t1sc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/ write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. table 18-2. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x 1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 0 output compare or pwm software compare only 0 1 0 1 toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1 x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare timer interface module (tim1) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 276 freescale semiconductor when elsxb and elsxa are both clear, channel x is not connected to an i/o port, and pin tchx is available as a general-purpose i/o pin. table 18-2 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. note after initially enabling a tim1 channel register for input capture operation and selecting the edge sensitivity, clear chxf to ignore any erroneous edge detection flags. tovx ? toggle-on-overflow bit when channel x is an output compare channel, this read/ write bit controls the behavior of the channel x output when the tim1 counter overflows. when c hannel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim1 counter overflow. 0 = channel x pin does not toggle on tim1 counter overflow. note when tovx is set, a tim1 counter overflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at 1, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 18-9 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. note the 100% pwm duty cycle is defined as a continuous high level if the pwm polarity is 1 and a continuous low level if the pwm polarity is 0. conversely, a 0% pwm duty cycle is defined as a continuous low level if the pwm polarity is 1 and a continuous high level if the pwm polarity is 0. figure 18-9. chxmax latency 18.8.5 tim1 channel registers these read/write registers contain the captured tim1 counter value of the input capture function or the output compare value of the output compare function. the state of the tim1 channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading the high byte of the tim1 channel x registers (t1chxh) inhibits input captures unt il the low byte (t1chxl) is read. output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare input/output registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 277 in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim1 channel x registers (t1chxh) inhibits output compares until the low byte (t1chxl) is written. address: $0026 t1ch0h bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset address: $0027 t1ch0l bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset address: $0029 t1ch1h bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset address: $02a t1ch1l bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 18-10. tim1 channel registers (t1ch0h/l:t1ch1h/l) timer interface module (tim1) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 278 freescale semiconductor mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 279 chapter 19 timer interface module (tim2) 19.1 introduction this section describes the timer interface module (t im2). the tim2 is a 6-channel timer that provides a timing reference with input capture, output compare, and pulse-width- modulation functions. figure 19-2 is a block diagram of the tim2. 19.2 features features of the tim2 include: ? six input capture/output compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action ? buffered and unbuffered pulse width modulation (pwm) signal generation ? programmable tim2 clock input ? 7-frequency internal bus clock prescaler selection ? external tim2 clock input (4-mhz maximum frequency) ? free-running or modulo up-count operation ? toggle any channel pin on overflow ? tim2 counter stop and reset bits 19.3 functional description figure 19-2 shows the tim2 structure. the central component of the tim2 is the 16-bit tim2 counter that can operate as a free-running count er or a modulo up-counter. the ti m2 counter provides the timing reference for the input capture and output compare functions. the tim2 counter modulo registers, t2modh:t2modl, control the modulo value of the tim2 counter. software can read the tim2 counter value at any time without affecting the counting sequence. the six tim2 channels are programmable independently as input capture or output compare channels. timer interface module (tim2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 280 freescale semiconductor figure 19-1. block diagram highlighting tim2 block and pins single breakpoint break module system integration module programmable timebase module monitor mode entry serial peripheral 6-channel timer interface module dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash ? 62,078 bytes user ram ? 2048 bytes monitor rom user flash vector space ? 52 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 rst (1) irq (1) interface module interrupt module computer operating properly module pta7/kbd7/ad15? 10-bit analog-to-digital converter module ptc6 (2) ptc5 (2) ptc4 (2, 3) ptc3 (2, 3) ptc2 (2, 3) ptc1/can rx (2, 3) ptc0/can tx (2, 3) ptd7/t2ch1 (2) ptd6/t2ch0 (2) ptd5/t1ch1 (2) ptd4/t1ch0 (2) ptd3/spsck (2) ptd2/mosi (2) ptd1/miso (2) ptd0/ss /mclk (2) pte1/rxd pte0/txd 2-channel timer interface module enhanced serial interface module security module power-on reset module memory map module configuration register 1?2 module power v ss v dd v ssa v dda 1. pin contains in tegrated pullup device. 2. ports are software configurable with pullup device if input port or pullup/pulldown device for keyboard input. 3. higher current drive port pins v ddad /v refh v ssad /v refl pte5?pte2 communications clock generator module cgmxfc phase locked loop 1?8 mhz oscillator portb ddrb ptb7/ad7? portf ddrf ptf7/t2ch5 module portg ddrg ptg7/ad23? ptf6/t2ch4 ptf5/t2ch3 ptf4/t2ch2 ptf3?pft0 (3) mscan module pta0/kbd0/ad8 (2) ptb0/ad0 ptg0/ad16 functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 281 figure 19-2. tim2 block diagram prescaler prescaler select tclk internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch t2ch0h:t2ch0l ms0a els0b els0a ptd6 tof toie inter- channel 0 t2modh:t2modl trst tstop tov0 ch0ie ch0max ms0b 16-bit counter bus clock t2ch0 t2ch1 t2ch2 t2ch3 logic rupt logic inter- rupt logic 16-bit comparator 16-bit latch t2ch1h:t2ch1l ms1a els1b els1a ptd7 channel 1 tov1 ch1ie ch1max logic inter- rupt logic 16-bit comparator 16-bit latch t2ch2h:t2ch2l ms2a els2b els2a ptf4 channel 2 tov2 ch2ie ch2max ms2b logic inter- rupt logic 16-bit comparator 16-bit latch t2ch3h:t2ch3l ms3a els3b els3a ptf5 channel 3 tov3 ch3ie ch3max logig inter- rupt logic 16-bit comparator 16-bit latch t2ch4h:t2ch4l ms4a els4b els4a ptf6 channel 4 tov4 ch4ie ch4max ms4b logic inter- rupt logic 16-bit comparator 16-bit latch t2ch5h:t2ch5l ms5a els5b els5a ptf7 channel 5 tov5 ch5ie ch5max logic inter- rupt logic t2ch4 t2ch5 ch0f ch1f ch2f ch3f ch4f ch5f ptd6/t2ch0 timer interface module (tim2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 282 freescale semiconductor addr. register name bit 7 6 5 4 3 2 1 bit 0 $002b tim2 status and control register (t2sc) see page 291. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 0 0 1 0 0 0 0 0 $002c tim2 counter register high (t2cnth) see page 292. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002d tim2 counter register low (t2cntl) see page 292. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $002e tim2 modulo register high (t2modh) see page 293. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $002f tim2 modulo register low (t2modl) see page 293. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0030 tim2 channel 0 status and control register (t2sc0) see page 293. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0031 tim2 channel 0 register high (t2ch0h) see page 297. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0032 tim2 channel 0 register low (t2ch0l) see page 297. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0033 tim2 channel 1 status and control register (t2sc1) see page 293. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 0 0 0 0 0 0 0 0 $0034 tim2 channel 1 register high (t2ch1h) see page 297. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0035 tim2 channel 1 register low (t2ch1l) see page 297. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0456 tim2 channel 2 status and control register (t2sc2) see page 293. read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 0 0 0 0 0 0 0 0 = unimplemented figure 19-3. tim2 i/o register summary (sheet 1 of 2) functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 283 $0457 tim2 channel 2 register high (t2ch2h) see page 297. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0458 tim2 channel 2 register low (t2ch2l) see page 297. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0459 tim2 channel 3 status and control register (t2sc3) see page 293. read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset: 0 0 0 0 0 0 0 0 $045a tim2 channel 3 register high (t2ch3h) see page 297. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $045b tim2 channel 3 register low (t2ch3l) see page 297. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $045c tim2 channel 4 status and control register (t2sc4) see page 293. read: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max write: 0 reset: 0 0 0 0 0 0 0 0 $045d tim2 channel 4 register high (t2ch4h) see page 297. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $045e tim2 channel 4 register low (t2ch4l) see page 297. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $045f tim2 channel 5 status and control register (t2sc5) see page 293. read: ch5f ch5ie 0 ms5a els5b els5a tov5 ch5max write: 0 reset: 0 0 0 0 0 0 0 0 $0460 tim2 channel 5 register high (t2ch5h) see page 297. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0461 tim2 channel 5 register low (t2ch5l) see page 297. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented figure 19-3. tim2 i/o register summary (sheet 2 of 2) timer interface module (tim2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 284 freescale semiconductor 19.3.1 tim2 counter prescaler the tim2 clock source can be one of the seve n prescaler outputs or the tim2 clock pin, t2ch0 . the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim2 status and control register select the tim2 clock source. 19.3.2 input capture an input capture function has thr ee basic parts: edge select logic, an input capture latch, and a 16-bit counter. two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the correspondi ng input capture edge detector senses a defined transition. the polarity of the active edge is programma ble. the level transition which triggers the counter transfer is defined by the corresponding input ed ge bits (elsxb and elsxa in t2sc0 through t2sc5 control registers with x referring to the active channel number). when an active edge occurs on the pin of an input capture channel, the tim2 latches the cont ents of the tim2 counter into the tim2 channel registers, t2chxh:t2chxl. input captures can generate tim2 cpu interrupt requests. software can determine that an input capture event has occurred by enabling input capture in terrupts or by polling the status flag bit. the free-running counter contents are transferred to the tim2 channel registers (t2chxh:t2chxl) (see 19.8.5 tim2 channel registers ) on each proper signal transition regardless of whether the tim2 channel flag (ch0f?ch5f in t2sc0?t2sc5 registers) is set or clear. when the status flag is set, a cpu interrupt is generated if enabled. the value of the count latched or ?captured? is the time of the event. because this value is stored in the input capture register when t he actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. however, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. by recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. to measure a perio d, two successive edges of the same polarity are captured. to measure a pulse width, two alternate polarity edges are captured. software should track the overflows at the 16-bit module counter to extend its range. another use for the input capture function is to establis h a time reference. in this case, an input capture function is used in conjuncti on with an output compare function. for example, to activate an output signal a specified number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. a number corresponding to the desired delay is added to this captured value and stored to an output compare register (see 19.8.5 tim2 channel registers ). because both input captures and output compares are refer enced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. reset does not affect the contents of the input capture channel (t2chxh:t2chxl) registers. 19.3.3 output compare with the output compare function, the tim2 can gener ate a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim2 can set, clear, or toggle the channel pin. output compares can generate tim2 cpu interrupt requests. functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 285 19.3.3.1 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 19.3.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the tim2 channel registers. an unsynchronized write to the tim2 channel regist ers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim2 over flow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim2 may pass the new value before it is written. use the following methods to synchronize unbuffer ed changes in the output compare value on channel x: ? when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. ? when changing to a larger output compare value, enable tim2 overflow interrupts and write the new value in the tim2 overflow interrupt routine. the tim2 overflow interrupt occurs at the end of the current counter overflow period. writing a larg er value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 19.3.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the t2ch0 pin. the tim2 channel registers of the linked pair alternately control the output. setting the ms0b bit in tim2 channel 0 status and cont rol register (t2sc0) links channel 0 and channel 1. the output compare value in the tim2 channel 0 registers initially controls the output on the t2ch0 pin. writing to the tim2 channel 1 registers enables the tim2 channel 1 registers to synchronously control the output after the tim2 overflows. at each subsequent overflow, the tim2 channel registers (0 or 1) that control the output are the ones written to last. t2sc0 controls and monitors the buffered output compare function, and tim2 channel 1 status and control regi ster (t2sc1) is unused. while the ms0b bit is set, the channel 1 pin, t2ch1, is availa ble as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the t2ch2 pin. the tim2 channel registers of the linked pair alternately control the output. setting the ms2b bit in tim2 channel 2 status and cont rol register (t2sc2) links channel 2 and channel 3. the output compare value in the tim2 channel 2 registers initially controls the output on the t2ch2 pin. writing to the tim2 channel 3 registers enables the tim2 channel 3 registers to synchronously control the output after the tim2 overflows. at each subsequent overflow, the tim2 channel registers (2 or 3) that control the output are the ones written to last. t2sc2 controls and monitors the buffered output compare function, and tim2 channel 3 status and control regi ster (t2sc3) is unused. while the ms2b bit is set, the channel 3 pin, t2ch3, is ava ilable as a general-purpose i/o pin. channels 4 and 5 can be linked to form a buffered output compare channel whose output appears on the t2ch4 pin. the tim2 channel registers of the linked pair alternately control the output. setting the ms4b bit in tim2 channel 4 status and cont rol register (t2sc4) links channel 4 and channel 5. the output compare value in the tim2 channel 4 registers initially controls the output on the t2ch4 pin. timer interface module (tim2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 286 freescale semiconductor writing to the tim2 channel 5 registers enables the tim2 channel 5 registers to synchronously control the output after the tim2 overflows. at each subsequent overflow, the tim2 channel registers (4 or 5) that control the output are the ones written to last. t2sc4 controls and monitors the buffered output compare function, and tim2 channel 5 status and control regi ster (t2sc5) is unused. while the ms4b bit is set, the channel 5 pin, t2ch5, is ava ilable as a general-purpose i/o pin. note in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 19.3.4 pulse widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim2 can generate a pwm signal. the value in the tim2 counter modulo registers determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the tim2 counter modulo registers. the time between overflows is the period of the pwm signal. as figure 19-4 shows, the output compare value in the tim2 channel registers determines the pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim2 to clear the channel pin on output compare if the polarity of the pwm pulse is 1 (elsxa = 0). program the tim2 to set the pin if the polarity of the pwm pulse is 0 (elsxa = 1). figure 19-4. pwm period and pulse width the value in the tim2 counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim2 counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is 000 (see 19.8.1 tim2 status and control register ). the value in the tim2 channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim2 channel registers produces a duty cycle of 128/256 or 50%. tchx period pulse width overflow overflow overflow output compare output compare output compare tchx polarity = 1 (elsxa = 0) polarity = 0 (elsxa = 1) functional description mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 287 19.3.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 19.3.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the tim2 channel registers. an unsynchronized write to the tim2 channel regi sters to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim2 overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim2 may pass the ne w value before it is written to the timer channel (t2chxh:t2chxl) registers. use the following methods to synchronize unbuffer ed changes in the pwm pulse width on channel x: ? when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. ? when changing to a longer pulse width, enable ti m2 overflow interrupts and write the new value in the tim2 overflow interrupt routine. the tim2 overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 19.3.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the t2ch0 pin. the tim2 channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim2 channel 0 status and cont rol register (t2sc0) links channel 0 and channel 1. the tim2 channel 0 registers initially control the pulse width on the t2ch0 pin. writing to the tim2 channel 1 registers enables the tim2 channel 1 regist ers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim2 channel registers (0 or 1) that control the pulse width are the ones written to la st. t2sc0 controls and monitors the buffered pwm function, and tim2 channel 1 status and control regi ster (t2sc1) is unused. while the ms0b bit is set, the channel 1 pin, t2ch1, is availa ble as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the t2ch2 pin. the tim2 channel registers of the linked pair alternately control the pulse width of the output. setting the ms2b bit in tim2 channel 2 status and cont rol register (t2sc2) links channel 2 and channel 3. the tim2 channel 2 registers initially control the pulse width on the t2ch2 pin. writing to the tim2 channel 3 registers enables the tim2 channel 3 regist ers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim2 channel registers (2 or 3) that control the pulse width are the ones written to la st. t2sc2 controls and monitors the buffered pwm timer interface module (tim2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 288 freescale semiconductor function, and tim2 channel 3 status and control regi ster (t2sc3) is unused. while the ms2b bit is set, the channel 3 pin, t2ch3, is ava ilable as a general-purpose i/o pin. channels 4 and 5 can be linked to form a buffered pwm channel whose output appears on the t2ch4 pin. the tim2 channel registers of the linked pair alternately control the pulse width of the output. setting the ms4b bit in tim2 channel 4 status and cont rol register (t2sc4) links channel 4 and channel 5. the tim2 channel 4 registers initially control the pulse width on the t2ch4 pin. writing to the tim2 channel 5 registers enables the tim2 channel 5 regist ers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim2 channel registers (4 or 5) that control the pulse width are the ones written to la st. t2sc4 controls and monitors the buffered pwm function, and tim2 channel 5 status and control regi ster (t2sc5) is unused. while the ms4b bit is set, the channel 5 pin, t2ch5, is ava ilable as a general-purpose i/o pin. note in buffered pwm signal generation, do not write pulse width values to the currently active channel registers. us er software should track the currently active channel to prevent writing a ne w value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 19.3.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim2 status and control register (t2sc): a. stop the tim2 counter by setting the tim2 stop bit, tstop. b. reset the tim2 counter and prescaler by setting the tim2 reset bit, trst. 2. in the tim2 counter modulo registers (t2modh:t2modl), write the value for the required pwm period. 3. in the tim2 channel x registers (t2chxh:t2chxl) , write the value for the required pulse width. 4. in tim2 channel x status and control register (t2scx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode se lect bits, msxb:msxa. (see table 19-2 .) b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (polarity 1 ? to clear output on compare) or 1:1 (polarity 0 ? to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 19-2 .) note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim2 status control register (t2sc), clear the tim2 stop bit, tstop. interrupts mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 289 setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim2 channel 0 registers (t2ch0h:t2ch0l) initially control the buffered pwm output. tim2 status control register 0 (t2sc0) controls and monitors the pwm si gnal from the linked channels. ms0b takes priority over ms0a. setting ms2b links channels 2 and 3 and configures them for buffered pwm operation. the tim2 channel 2 registers (t2ch2h:t2ch2l) initially control the buffered pwm output. tim2 status control register 2 (t2sc2) controls and monitors the pwm si gnal from the linked channels. ms2b takes priority over ms2a. setting ms4b links channels 4 and 5 and configures them for buffered pwm operation. the tim2 channel 4 registers (t2ch4h:t2ch4l) initially control the buffered pwm output. tim2 status control register 4 (t2sc4) controls and monitors the pwm si gnal from the linked channels. ms4b takes priority over ms4a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim2 overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. (see 19.8.4 tim2 channel status and control registers .) 19.4 interrupts the following tim2 sources can generate interrupt requests: ? tim2 overflow flag (tof) ? the tof bit is set when the tim2 counter reaches the modulo value programmed in the tim2 counter modulo registers. the tim2 overflow interrupt enable bit, toie, enables tim2 overflow interrupt requests. tof and toie are in the tim2 status and control register. ? tim2 channel flags (ch5f:ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim2 cpu interr upt requests are controlled by the channel x interrupt enable bit, chxie. 19.5 low-power modes the wait and stop instructions put the mcu in low-power standby modes. 19.5.1 wait mode the tim2 remains active after the execution of a wait instruction. in wait mode, the tim2 registers are not accessible by the cpu. any enabled cpu interrupt request from the tim2 can bring the mcu out of wait mode. if tim2 functions are not required during wait mode, reduce power consumption by stopping the tim2 before executing the wait instruction. 19.5.2 stop mode the tim2 is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tim2 counter. tim2 operation resumes when the mcu exits stop mode. timer interface module (tim2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 290 freescale semiconductor 19.6 tim2 during break interrupts a break interrupt stops the tim2 counter and inhibits input captures. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see 15.7.3 break flag control register .) to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if so ftware does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 19.7 i/o signals port d shares two of its pins with the tim2. port f s hares four of its pins with the tim2. ptd6/t2ch0 is an external clock input to the tim2 prescaler. the six tim2 channel i/o pins are ptd6/t2ch0, ptd7/t2ch1, ptf4/t2ch2, ptf5/t2ch3, ptf6/t2ch4, and ptf7/t2ch5. 19.7.1 tim2 cl ock pin (t2ch0) t2ch0 is an external clock input that can be the clock source for the tim2 counter instead of the prescaled internal bus clock. select the t2ch0 input by writing 1s to the three prescaler select bits, ps[2:0]. (see 19.8.1 tim2 status and control register .) the minimum tclk puls e width is specified in 21.14 timer interface module characteristics . the maximum tclk frequency is the least: 4 mhz or bus frequency 2. when the ptd6/t2ch0 pin is the tim2 clock input, it is an input regardless of the state of the ddrd6 bit in data direction register d. 19.7.2 tim2 channel i/o pins (t2ch5:t2ch2 and t2ch1:t2ch0) each channel i/o pin is programmable independently as an input capture pin or an output compare pin. t2ch0, t2ch2, and t2ch4 can be configured as buffered output compare or buffered pwm pins. 19.8 i/o registers these i/o registers control and monitor tim2 operation: ? tim2 status and control register (t2sc) ? tim2 counter registers (t2cnth:t2cntl) ? tim2 counter modulo registers (t2modh:t2modl) ? tim2 channel status and control registers (t2s c0, t2sc1, t2sc2, t2sc3, t2sc4, and t2sc5) ? tim2 channel registers (t2ch0h:t2ch0l, t2ch1h:t2ch1l, t2ch2h:t2ch2l, t2ch3h:t2ch3l, t2ch4h:t2ch4l, and t2ch5h:t2ch5l) i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 291 19.8.1 tim2 status and control register the tim2 status and control register: ? enables tim2 overflow interrupts ? flags tim2 overflows ? stops the tim2 counter ? resets the tim2 counter ? prescales the tim2 counter clock tof ? tim2 overflow flag bit this read/write flag is set when the tim2 counter resets reaches the modulo value programmed in the tim2 counter modulo registers. clear tof by reading the tim2 status and control register when tof is set and then writing a 0 to tof. if another tim2 overflow occurs before the clearing sequence is complete, then writing 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears t he tof bit. writing a 1 to tof has no effect. 1 = tim2 counter has reached modulo value 0 = tim2 counter has not reached modulo value toie ? tim2 overflow interrupt enable bit this read/write bit enables tim2 overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tim2 overflow interrupts enabled 0 = tim2 overflow interrupts disabled tstop ? tim2 stop bit this read/write bit stops the tim2 counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim2 counter until software clears the tstop bit. 1 = tim2 counter stopped 0 = tim2 counter active note do not set the tstop bit before entering wait mode if the tim2 is required to exit wait mode. also when the tstop bit is set and the timer is configured for input capture operation, i nput captures are inhibited until the tstop bit is cleared. trst ? tim2 reset bit setting this write-only bit resets the tim2 counter a nd the tim2 prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim2 counter is reset and always reads as 0. reset clears the trst bit. 1 = prescaler and tim2 counter cleared 0 = no effect address: $002b bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 19-5. tim2 status and control register (t2sc) timer interface module (tim2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 292 freescale semiconductor note setting the tstop and trst bits simultaneously stops the tim2 counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select either the t2ch0 pin or one of the seven prescaler outputs as the input to the tim2 counter as table 19-1 shows. reset clears the ps[2:0] bits. 19.8.2 tim2 counter registers the two read-only tim2 counter registers contain the high and low bytes of the value in the tim2 counter. reading the high byte (t2cnth) latches the contents of the low byte (t2cntl) into a buffer. subsequent reads of t2cnth do not affect the latched t2cntl value until t2cntl is read. reset clears the tim2 counter registers. setting the tim2 reset bit (trst) also clears the tim2 counter registers. note if t2cnth is read during a break interrupt, be sure to unlatch t2cntl by reading t2cntl before exiting the break interrupt. otherwise, t2cntl retains the value latched during the break. table 19-1. prescaler selection ps[2:0] tim2 clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 t2ch0 address: $002c t2cnth bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $002d t2cntl bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 19-6. tim2 counter registers (t2cnth and t2cntl) i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 293 19.8.3 tim2 counter modulo registers the read/write tim2 modulo registers contain the modulo value for the tim2 counter. when the tim2 counter reaches the modulo value, the overflow fl ag (tof) becomes set, and the tim2 counter resumes counting from $0000 at the next timer clock. writing to the high byte (t2modh) inhibits the tof bit and overflow interrupts until the low byte (t2modl) is wr itten. reset sets the tim2 counter modulo registers. note reset the tim2 counter before writing to the tim2 counter modulo registers. 19.8.4 tim2 channel status and control registers each of the tim2 channel status and control registers: ? flags input captures and output compares ? enables input capture and output compare interrupts ? selects input capture, output compare, or pwm operation ? selects high, low, or toggling output on output compare ? selects rising edge, falling edge, or any edge as the active input capture trigger ? selects output toggling on tim2 overflow ? selects 0% and 100% pwm duty cycle ? selects buffered or unbuffered output compare/pwm operation address: $002e t2modh bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $002f t2modl bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 19-7. tim2 counter modulo registers (t2modh and t2modl) address: $0030 t2sc0 bit 765432 1bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 = unimplemented figure 19-8. tim2 channel status and control registers (t2sc0:t2sc5) timer interface module (tim2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 294 freescale semiconductor chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the tim2 counter registers matches the value in the tim2 channel x registers. when chxie = 1, clear chxf by reading tim2 channel x status and control register with chxf set, and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tim2 cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled address: $0033 t2sc1 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 address: $0456 t2sc2 bit 7654321bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 address: $0459 t2sc3 bit 7654321bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 address: $045c t2sc4 bit 7654321bit 0 read: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max write: 0 reset:00000000 address: $045f t2sc5 bit 7654321bit 0 read: ch5f ch5ie 0 ms5a els5b els5a tov5 ch5max write: 0 reset:00000000 = unimplemented figure 19-8. tim2 channel status and control registers (t2sc0:t2sc5) (continued) i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 295 msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim2 channel 0, tim2 channel 2, and tim2 channel 4 status and control registers. setting ms0b disables the channel 1 status and control register and reverts t2ch1 pin to general-purpose i/o. setting ms2b disables the channel 3 status and control register and reverts t2ch3 pin to general-purpose i/o. setting ms4b disables the channel 5 status and control register and reverts t2ch5 pin to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:elsxa 00, this read/write bit selects eit her input capture operation or unbuffered output compare/pwm operation. (see table 19-2 .) 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:elsxa = 00, this read/write bit selects the initial output level of the t2chx pin once pwm, input capture, or output compare operation is enabled. (see table 19-2 .) reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim2 status and control register (t2sc). table 19-2. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x 1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 0 output compare or pwm software compare only 0 1 0 1 toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1 x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare timer interface module (tim2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 296 freescale semiconductor elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/ write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port d or port f, and pin ptdx/t2chx or pin ptfx/t2chx is av ailable as a general- purpose i/o pin. table 19-2 shows how elsxb and elsxa work. reset cl ears the elsxb and elsxa bits. note after initially enabling a tim2 channel register for input capture operation and selecting the edge sensitivity, clear chxf to ignore any erroneous edge detection flags. tovx ? toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim2 counter overflows. when ch annel x is an input capt ure channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim2 counter overflow. 0 = channel x pin does not toggle on tim2 counter overflow. note when tovx is set, a tim2 counter overflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at a 1 and clear output on compare is selected, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 19-9 shows, the chxmax bit takes effect in the cycle after it is set or clear ed. the output stays at 100% duty cycle level until the cycle after chxmax is cleared. note the 100% pwm duty cycle is defined as a continuous high level if the pwm polarity is 1 and a continuous low level if the pwm polarity is 0. conversely, a 0% pwm duty cycle is defined as a continuous low level if the pwm polarity is 1 and a continuous high level if the pwm polarity is 0. figure 19-9. chxmax latency output overflow ptdx/t2chx period chxmax overflow overflow overflow overflow compare output compare output compare output compare i/o registers mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 297 19.8.5 tim2 channel registers these read/write registers contain the captured tim2 counter value of the input capture function or the output compare value of the output compare function. the state of the tim2 channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading the high byte of the tim2 channel x registers (t2chxh) inhibits input captures unt il the low byte (t2chxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim2 channel x registers (t2chxh) inhibits output compares until the low byte (t2chxl) is written. address: $0031 t2ch0h bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset address: $0032 t2ch0l bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset address: $0034 t2ch1h bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset address: $0035 t2ch1l bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset address: $0457 t2ch2h bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset address: $0458 t2ch2l bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 19-10. tim2 channel registers (t2ch0h/l:t2ch5h/l) timer interface module (tim2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 298 freescale semiconductor address: $045a t2ch3h bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset address: $045b t2ch3l bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset address: $045d t2ch4h bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset address: $045e t2ch4l bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset address: $0460 t2ch5h bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset address: $0461 t2ch5l bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 19-10. tim2 channel registers (t2ch0h/l:t2ch5h/l) (continued) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 299 chapter 20 development support 20.1 introduction this section describes the break module, the mo nitor module (mon), and the monitor mode entry methods. 20.2 break module (brk) the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. features of the break module include: ? accessible input/output (i/o) registers during the break interrupt ? central processor unit (cpu) generated break interrupts ? software-generated break interrupts ? computer operating properly (cop ) disabling during break interrupts 20.2.1 functional description when the internal address bus matches the value writt en in the break address registers, the break module issues a breakpoint signal (bkpt ) to the system integration module (sim). the sim then causes the cpu to load the instruction register with a software interrupt instruction (swi). the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: ? a cpu generated address (the address in the program counter) matches the contents of the break address registers. ? software writes a 1 to the brka bit in the break status and control register. when a cpu generated address matches the contents of t he break address registers, the break interrupt is generated. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the microcontroller unit (mcu) to normal operation. figure 20-2 shows the structure of the break module. figure 20-3 provides a summary of the i/o registers. development support mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 300 freescale semiconductor figure 20-1. block diagram highlighting brk and mon blocks single breakpoint break module system integration module programmable timebase module monitor mode entry serial peripheral 6-channel timer interface module dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash ? 62,078 bytes user ram ? 2048 bytes monitor rom user flash vector space ? 52 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 rst (1) irq (1) interface module interrupt module computer operating properly module pta7/kbd7/ad15? 10-bit analog-to-digital converter module ptc6 (2) ptc5 (2) ptc4 (2, 3) ptc3 (2, 3) ptc2 (2, 3) ptc1/can rx (2, 3) ptc0/can tx (2, 3) ptd7/t2ch1 (2) ptd6/t2ch0 (2) ptd5/t1ch1 (2) ptd4/t1ch0 (2) ptd3/spsck (2) ptd2/mosi (2) ptd1/miso (2) ptd0/ss /mclk (2) pte1/rxd pte0/txd 2-channel timer interface module enhanced serial interface module security module power-on reset module memory map module configuration register 1?2 module power v ss v dd v ssa v dda 1. pin contains in tegrated pullup device. 2. ports are software configurable with pullup device if input port or pullup/pulldow n device for keyboard input. 3. higher current drive port pins v ddad /v refh v ssad /v refl pte5?pte2 communications clock generator module cgmxfc phase locked loop 1?8 mhz oscillator portb ddrb ptb7/ad7? portf ddrf ptf7/t2ch5 module portg ddrg ptg7/ad23? ptf6/t2ch4 ptf5/t2ch3 ptf4/t2ch2 ptf3?pft0 (3) mscan module pta0/kbd0/ad8 (2) ptb0/ad0 ptg0/ad16 break module (brk) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 301 figure 20-2. break module block diagram addr.register name bit 7654321bit 0 $fe00 break status register (bsr) see page 304. read: rrrrrr sbsw r write: note (1) reset: 0 $fe03 break flag control register (bfcr) see page 304. read: bcferrrrrrr write: reset: 0 $fe09 break address high register (brkh) see page 303. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $fe0a break address low register (brkl) see page 303. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $fe0b break status and control register (brkscr) see page 303. read: brke brka 000000 write: reset:00000000 1. writing a 0 clears sbsw. = unimplemented r = reserved figure 20-3. break i/o register summary address bus[15:8] address bus[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high address bus[15:0] bkpt (to sim) development support mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 302 freescale semiconductor when the internal address bus matches the value writt en in the break address registers or when software writes a 1 to the brka bit in the break status and c ontrol register, the cpu starts a break interrupt by: ? loading the instruction register with the swi instruction ? loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt timing is: ? when a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. ? when a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. ? when software writes a 1 to the brka bit, the break interrupt occurs just before the next instruction is executed. by updating a break address and clearing the brka bit in a break interrupt routine, a break interrupt can be generated continuously. caution a break address should be placed at the address of the instruction opcode. when software does not change the break address and clears the brka bit in the first break interrupt routi ne, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers. 20.2.1.1 flag protection during break interrupts the system integration module (sim) controls whether or not module status bits can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see 15.7.3 break flag control register and the break interrupts subsection for each module. 20.2.1.2 tim during break interrupts a break interrupt stops the timer counter and inhibits input captures. 20.2.1.3 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 20.2.2 break module registers these registers control and monitor operation of the break module: ? break status and control register (brkscr) ? break address register high (brkh) ? break address register low (brkl) ? break status register (bsr) ? break flag control register (bfcr) break module (brk) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 303 20.2.2.1 break status and control register the break status and control register (brkscr) contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break address re gister matches. clear brke by writing a 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a 1 to brka generates a break interrupt. clear brka by writing a 0 to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match 20.2.2.2 break address registers the break address registers (brkh and brkl) contai n the high and low bytes of the desired breakpoint address. reset clears the break address registers. address: $fe0b bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 20-4. break status and control register (brkscr) address: $fe09 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 figure 20-5. break address register high (brkh) address: $fe0a bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 20-6. break address register low (brkl) development support mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 304 freescale semiconductor 20.2.2.3 break status register the break status register (bsr) contains a flag to i ndicate that a break caused an exit from wait mode. this register is only used in emulation mode. sbsw ? sim break stop/wait sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. 1 = wait mode was exited by break interrupt 0 = wait mode was not exited by break interrupt 20.2.2.4 break flag control register the break control register (bfcr) contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break 20.2.3 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. if enabled, the break module will remain enabled in wait and st op modes. however, since the internal address bus does not increment in these modes, a break interrupt will never be triggered. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a 0 clears sbsw. figure 20-7. break status register (bsr) address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r = reserved figure 20-8. break flag control register (bfcr) monitor module (mon) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 305 20.3 monitor module (mon) the monitor module allows debugging and programmin g of the microcontroller unit (mcu) through a single-wire interface with a host computer. monitor mode entry can be achieved without use of the higher test voltage, v tst , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware requirements for in-circuit programming. features of the monitor module include: ? normal user-mode pin functionality ? one pin dedicated to serial communi cation between mcu and host computer ? standard non-return-to-zero (nrz) communication with host computer ? standard communication baud rate (7200 @ 2-mhz bus frequency) ? execution of code in random-a ccess memory (ram) or flash ? flash memory security feature (1) ? flash memory programming interface ? monitor mode entry without high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) ? normal monitor mode entry if v tst is applied to irq 20.3.1 functional description figure 20-9 shows a simplified diagram of the monitor mode. the monitor module receives and execut es commands from a host computer. figure 20-10 and figure 20-11 show example circuits used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute code downloaded into ram by a host computer wh ile most mcu pins retain normal operating mode functions. all communicati on between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pullup resistor. table 20-1 shows the pin conditions for entering monitor mode. as specified in the table, monitor mode may be entered after a power-on reset (por) and will allow communication at 7200 baud provided one of the following sets of conditions is met: ? if $fffe and $ffff does not contain $ff (programmed state): ? the external clock is 4.0 mhz (7200 baud) ?ptb4 = low ?irq = v tst ? if $fffe and $ffff do not contain $ff (programmed state): ? the external clock is 8.0 mhz (7200 baud) ? ptb4 = high ? irq = v tst ? if $fffe and $ffff contain $ff (erased state): ? the external clock is 8.0 mhz (7200 baud) ?irq = v dd (this can be implemented through the internal irq pullup) or v ss 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users. development support mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 306 freescale semiconductor figure 20-9. simplified monitor mode entry flowchart monitor mode entry por reset pta0 = 1, pta1 = 0, ptb0 = 1, and ptb1 = 0? irq = v tst ? pta0 = 1, pta1 = 0, reset vector blank? yes no yes no forced monitor mode normal user mode normal monitor mode invalid user mode no no host sends 8 security bytes is reset por? yes yes yes no are all security bytes correct? no yes enable flash disable flash execute monitor code does reset occur? conditions from table 20-1 debugging and flash programming (if flash is enabled) monitor module (mon) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 307 figure 20-10. normal monitor mode circuit figure 20-11. forced monitor mode 10 k 10 k 10 k 10 k rst irq pta0 osc1 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 v+ v? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k v ss 0.1 f v dd c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + + + 1 f v dd n.c. v cc gnd 1 k osc2 27 pf 27 pf 8 mhz 10 m v dda ptb4 ptb0 ptb1 pta1 v ssa v dd mc68hc908gz60 9.1 v v ddad v ssad 10 k rst irq pta0 osc1 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 v+ v? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k 0.1 f c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + + + 1 f v dd n.c. v cc gnd osc2 27 pf 27 pf 8 mhz 10 m ptb4 ptb0 ptb1 pta1 mc68hc908gz60 n.c. n.c. n.c. n.c. v dd v dda v ddad v ss v ssa v ssad development support mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 308 freescale semiconductor enter monitor mode with pin configuration shown in table 20-1 by pulling rst low and then high. the rising edge of rst latches monitor mode. once monitor mode is latched, the levels on the port pins except pta0 can change. once out of reset, the mcu waits for the host to send eight security bytes (see 20.3.2 security ). after the security bytes, the mcu sends a break signal (10 consecut ive 0s) to the host, indicating that it is ready to receive a command. table 20-1. monitor mode signal requirements and options mode irq rst reset vector serial communication mode selection divider pll cop communication speed pta0 pta1 ptb0 ptb1 ptb4 external clock bus frequency baud rate normal monitor v tst v dd or v tst x 1 0 1 0 0 off disabled 4.0 mhz 2.0 mhz 7200 v tst v dd or v tst x 1 0 1 0 1 off disabled 8.0 mhz 2.0 mhz 7200 forced monitor v dd or v ss v dd $ff (blank) 1 0 x x x off disabled 8.0 mhz 2.0 mhz 7200 user v dd or v ss v dd or v tst not $ff x x x x x x enabled x x x mon08 function [pin no.] v tst [6] rst [4] ? com [8] ssel [10] mod0 [12] mod1 [14] div4 [16] ?? osc1 [13] ?? 1. pta0 must have a pullup resistor to v dd in monitor mode. 2. communication speed in the t able is an example to obtain a baud rate of 7200 . baud rate using exter nal oscillator is bus frequency / 278. 3. external clock is a 4.0 mhz or 8.0 mhz crystal on osc1 and osc2 or a canned oscillator on osc1. 4. x = don?t care 5. mon08 pin refers to p&e microcomputer s ystems? mon08-cyclone 2 by 8-pin connector. nc 1 2 gnd nc 3 4 rst nc 5 6 irq nc 7 8 pta0 nc 9 10 pta1 nc 11 12 ptb0 osc1 13 14 ptb1 v dd 15 16 ptb4 monitor module (mon) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 309 20.3.1.1 normal monitor mode if v tst is applied to irq and ptb4 is low upon monitor mode entr y, the bus frequency is a divide-by-two of the input clock. if ptb4 is high with v tst applied to irq upon monitor mode entry, the bus frequency will be a divide-by-four of the input clock. holding the ptb4 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if v tst is applied to irq . in this event, the cgmout frequency is equal to the cgmxclk frequency, and the osc1 input directly generates internal bus clocks. in this case, the osc1 signal mu st have a 50% duty cycle at maximum bus frequency. when monitor mode was entered with v tst on irq , the computer operating properly (cop) is disabled as long as v tst is applied to either irq or rst . this condition states that as long as v tst is maintained on the irq pin after entering monitor mode, or if v tst is applied to rst after the initial reset to get into monitor mode (when v tst was applied to irq ), then the cop will be disabled. in the latter situation, after v tst is applied to the rst pin, v tst can be removed from the irq pin in the interest of freeing the irq for normal functionality in monitor mode. 20.3.1.2 forced monitor mode if entering monitor mode without high voltage on irq , then all port b pin requirements and conditions, including the ptb4 frequency divisor selection, are not in effect. this is to reduce circuit requirements when performing in-circuit programming. note if the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (por). once the reset vector has been programmed, the traditional method of applying a voltage, v tst , to irq must be used to enter monitor mode. an external oscillator of 8 mhz is required for a baud rate of 7200, as the internal bus frequency is automatically set to the external frequency divided by four. when the forced monitor mode is entered the cop is always disabled regardless of the state of irq or rst . 20.3.1.3 monitor vectors in monitor mode, the mcu uses different vectors for reset, swi (software interrupt), and break interrupt than those for user mode. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. table 20-2 summarizes the differences be tween user mode and monitor mode. table 20-2. mode differences modes functions reset vector high reset vector low break vector high break vector low swi vector high swi vector low user $fffe $ffff $fffc $fffd $fffc $fffd monitor $fefe $feff $fefc $fefd $fefc $fefd development support mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 310 freescale semiconductor 20.3.1.4 data format communication with the monitor rom is in standard non-return-to-zero (nrz) ma rk/space data format. transmit and receive baud rates must be identical. figure 20-12. monitor data format 20.3.1.5 break signal a start bit (0) followed by nine 0 bits is a break signal . when the monitor receives a break signal, it drives the pta0 pin high for the duration of approximately two bits and then echoes back the break signal. figure 20-13. break transaction 20.3.1.6 baud rate the communication baud rate is controlled by the crystal frequency or external clock and the state of the ptb4 pin (when irq is set to v tst ) upon entry into monitor mode. if monitor mode was entered with v dd on irq and the reset vector blank, then the baud rate is independent of ptb4. table 20-1 also lists external frequencies required to achieve a standard baud rate of 7200 bps. the effective baud rate is the bus fr equency divided by 278. if using a crys tal as the clock source, be aware of the upper frequency limit that the in ternal clock module can handle. see 21.7 5.0-volt control timing or 21.8 3.3-volt control timing for this limit. 20.3.1.7 commands the monitor rom firmware uses these commands: ? read (read memory) ? write (write memory) ? iread (indexed read) ? iwrite (indexed write) ? readsp (read stack pointer) ? run (run user program) the monitor rom firmware echoes each received byte back to the pta0 pin for error checking. an 11-bit delay at the end of each command allows the host to send a break character to cancel the command. a delay of two bit times occurs before each echo and before read, iread, or readsp data is returned. the data returned by a read command appears after the echo of the last byte of the command. note wait one bit time after each echo before sending the next byte. bit 5 start bit bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 7 bit 0 bit 6 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit approximately 2 bits delay before zero echo monitor module (mon) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 311 figure 20-14. read transaction figure 20-15. write transaction a brief description of each monitor mode command is given in table 20-3 through table 20-8 . table 20-3. read (read memory) command description read byte from memory operand 2-byte address in high-byte:low-byte order data returned returns contents of specified address opcode $4a command sequence read read echo from host address high address high address low address low data return 13, 2 11 4 4 notes: 2 = data return delay, approximately 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 44 1 = echo delay, approximately 2 bit times write write echo from host address high address high address low address low data data notes: 2 = cancel command delay, 11 bit times 3 = wait 1 bit time before sending next byte. 11 3 11 3 3 32, 3 1 = echo delay, approximately 2 bit times read read echo sent to monitor address high address high address low data return address low development support mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 312 freescale semiconductor a sequence of iread or iwrite commands can acce ss a block of memory sequentially over the full 64-kbyte memory map. table 20-4. write (write memory) command description write byte to memory operand 2-byte address in high-byte:low-byte order; low byte followed by data byte data returned none opcode $49 command sequence table 20-5. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand none data returned returns contents of next two addresses opcode $1a command sequence table 20-6. iwrite (indexed write) command description write to last address accessed + 1 operand single data byte data returned none opcode $19 command sequence write write echo from host address high address high address low address low data data iread iread echo from host data return data iwrite iwrite echo data data from host monitor module (mon) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 313 the mcu executes the swi and pshh instructions when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instru ctions. before sending th e run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command returns the incremented stack pointer value, sp + 1. the high and low bytes of the program counter are at addresses sp + 5 and sp + 6. figure 20-16. stack pointer at monitor mode entry table 20-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high-byte:low-byte order opcode $0c command sequence table 20-8. run (run user program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence readsp readsp echo from host sp return sp high low run run echo from host condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7 development support mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 314 freescale semiconductor 20.3.2 security a security feature discourages unauthorized reading of flash locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locations $fff6?$fffd contain user-defined data. note do not leave locations $fff6?$fffd bl ank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the powe r-on reset for the host to send the eight security bytes on pin pta0. if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all flash locations and execute code from flash. security remains bypassed until a power-on reset occurs. if the reset wa s not a power-on reset, security remains bypassed and security code entry is not required. see figure 20-17 . upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a flash location returns an invalid value and trying to execute code from flash causes an illegal address reset. after receiving the eight secu rity bytes from the host, the mcu transmits a break character, signifying that it is ready to receive a command. note the mcu does not transmit a break char acter until after the host sends the eight security bytes. figure 20-17. monitor mode entry timing to determine whether the security code entered is correct, check to see if bit 6 of ram address $40 is set. if it is, then the correct security code has been entered and flash can be accessed. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. after failing the securi ty sequence, the flash module can also be mass erased by executing an erase routine that was downl oaded into internal ram. the mass erase operation clears the security code locations so that all eight security bytes become $ff (blank). byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 rst v dd 4096 + 32 cgmxclk cycles 5 1 4 1 1 2 1 break notes: 2 = data return delay, approximately 2 bit times 4 = wait 1 bit time before sending next byte 4 from host from mcu 1 = echo delay, approximately 2 bit times 5 = wait until the monitor rom runs mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 315 chapter 21 electrical specifications 21.1 introduction this section contains electrical and timing specifications. 21.2 absolute maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to 21.5 5.0-vdc electrical characteristics for guaranteed operating conditions. note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). characteristic (1) 1. voltages referenced to v ss symbol value unit supply voltage v dd ?0.3 to + 6.0 v input voltage v in v ss ? 0.3 to v dd + 0.3 v maximum current per pin excluding those specified below i 15 ma maximum current for pins ptc0?ptc4 i ptc0?ptc4 25 ma maximum current into v dd i mvdd 150 ma maximum current out of v ss i mvss 150 ma storage temperature t stg ?55 to +150 c electrical specifications mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 316 freescale semiconductor 21.3 functional operating range 21.4 thermal characteristics characteristic symbol value unit operating temperature range t a ?40 to +125 c operating voltage range v dd 5.0 10% 3.3 10% v characteristic symbol value unit thermal resistance 32-pin lqfp 48-pin lqfp 64-pin qfp ja 95 95 54 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd v dd ) + p i/o = k/(t j + 273 c ) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . k p d (t a + 273 c) + p d 2 ja w / c average junction temperature t j t a + (p d ja ) c 5.0-vdc electrical characteristics mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 317 21.5 5.0-vdc electrical characteristics characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?2.0 ma) all i/o pins (i load = ?10.0 ma) all i/o pins (i load = ?20.0 ma) pins ptc0?ptc4, ptf0?ptf3 only maximum combined i oh for port pta7?pta3, port ptc0?ptc1, port e, port ptd0?ptd3, port ptf0?ptf3, port ptg4?ptg7 maximum combined i oh for port pta2?pta0, port b, port ptc2?ptc6, port ptd4?ptd7, port ptf4?ptf7, port ptg0?ptg3 maximum total i oh for all port pins v oh v oh v oh i oh1 i oh2 i oht v dd ? 0.8 v dd ? 1.5 v dd ? 1.5 ? ? ? ? ? ? ? ? ? ? ? ? 50 50 100 v v v ma ma ma output low voltage (i load = 1.6 ma) all i/o pins (i load = 10 ma) all i/o pins (i load = 20 ma) pins ptc0?ptc4, ptf0?ptf3 only maximum combined i oh for port pta7?pta3, port ptc0?ptc1, port e, port ptd0?ptd3, port ptf0?ptf3, port ptg4?ptg7 maximum combined i oh for port pta2?pta0, port b, port ptc2?ptc6, port ptd4?ptd7, port ptf4?ptf7, port ptg0?ptg3 maximum total i ol for all port pins v ol v ol v ol i ol1 i ol2 i olt ? ? ? ? ? ? ? ? ? ? ? ? 0.4 1.5 1.5 50 50 100 v v v ma ma ma input high voltage all ports, irq , rst , osc1 v ih 0.7 v dd ? v dd v input low voltage all ports, irq , rst , osc1 v il v ss ? 0.2 v dd v v dd supply current run (3) wait (4) stop (5) stop with tbm enabled (6) stop with lvi and tbm enabled (6) stop with lvi i dd ? ? ? ? ? ? 20 6 0.6 1 1.25 250 30 12 10 1.25 1.6 350 ma ma a ma ma a dc injection current (7) (8) (9) (10) single pin limit v in > v dd v in < v ss total mcu limit, includes sum of all stressed pins v in > v dd v in < v ss i ic 0 0 0 0 ? ? ? ? 2 ?0.2 25 ?5 ma i/o ports hi-z leakage current (11) i il 0? 1 a continued on next page electrical specifications mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 318 freescale semiconductor pullup/pulldown resistors (as input only) ports pta7/kbd7?pta0/kbd0, ptc6?ptc0/can tx , ptd7/t2ch1?ptd0/ss r pu 20 45 65 k capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf monitor mode entry voltage v tst v dd + 2.5 ? v dd + 4.0 v low-voltage inhibit, trip falling voltage v tripf 3.90 4.25 4.50 v low-voltage inhibit, trip rising voltage v tripr 4.0 4.35 4.60 v low-voltage inhibit reset/recover hysteresis (v tripf + v hys = v tripr ) v hys ?100 ?mv por rearm voltage (12) v por 0 ? 100 mv por reset voltage (13) v porrst 0 700 800 mv por rise time ramp rate (14) r por 0.035 ? ? v/ms 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t a (min) to t a (max), unless otherwise noted 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f osc = 32 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f osc = 32 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . measured with cgm and lvi enabled. 5. stop i dd is measured with osc1 = v ss . all inputs 0.2 v from rail. no dc loads . less than 100 pf on all outputs. all ports configured as inputs. typical values at midpoint of voltage range, 25c only. 6. stop i dd with tbm enabled is measured using an external square wave clock source (f osc = 8 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all inputs configured as inputs. 7. this parameter is characterized and not tested on each device. 8. all functional non-supply pins are internally clamped to v ss and v dd . 9. input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative cl amp voltages, then use the la rger of the two values. 10. power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consumin g power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 11. pullups and pulldowns are disabled . port b leakage is specified in 21.10 5.0-volt adc characteristics . 12. maximum is highest voltage that por is guaranteed. 13. maximum is highest voltage that por is possible. 14. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. characteristic (1) symbol min typ (2) max unit 3.3-vdc electrical characteristics mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 319 21.6 3.3-vdc electrical characteristics characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?0.6 ma) all i/o pins (i load = ?4.0 ma) all i/o pins (i load = ?10.0 ma) pins ptc0?ptc4, ptf0?ptf3 only maximum combined i oh for port pta7?pta3, port ptc0?ptc1, port e, port ptd0?ptd3, port ptf0?ptf3, port ptg4?ptg7 maximum combined i oh for port pta2?pta0, port b, port ptc2?ptc6, port ptd4?ptd7 port ptf4?ptf7, port ptg0?ptg3 maximum total i oh for all port pins v oh v oh v oh i oh1 i oh2 i oht v dd ? 0.3 v dd ? 1.0 v dd ? 1.0 ? ? ? ? ? ? ? ? ? ? ? ? 30 30 60 v v v ma ma ma output low voltage (i load = 0.5 ma) all i/o pins (i load = 5 ma) all i/o pins (i load = 10 ma) pins ptc0?ptc4, ptf0?ptf3 only maximum combined i oh for port pta7?pta3, port ptc0?ptc1, port e, port ptd0?ptd3 port ptf0?ptf3, port ptg4?ptg7 maximum combined i oh for port pta2?pta0, port b, port ptc2?ptc6, port ptd4?ptd7 port ptf4?ptf7, port ptg0?ptg3 maximum total i ol for all port pins v ol v ol v ol i ol1 i ol2 i olt ? ? ? ? ? ? ? ? ? ? ? ? 0.3 1.0 0.8 30 30 60 v v v ma ma ma input high voltage all ports, irq , rst , osc1 v ih 0.7 v dd ? v dd v input low voltage all ports, irq , rst , osc1 v il v ss ? 0.3 v dd v v dd supply current run (3) wait (4) stop (5) stop with tbm enabled (6) stop with lvi and tbm enabled (6) stop with lvi i dd ? ? ? ? ? ? 8 3 0.5 500 700 200 12 6 6 700 900 300 ma ma a a a a dc injection current (7) (8) (9) (10) single pin limit v in > v dd v in < v ss total mcu limit, includes sum of all stressed pins v in > v dd v in < v ss i ic 0 0 0 0 ? ? ? ? 2 ?0.2 25 ?5 ma i/o ports hi-z leakage current (11) i il 0? 1 a continued on next page electrical specifications mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 320 freescale semiconductor pullup/pulldown resistors (as input only) ports pta7/kbd7?pta0/kbd0, ptc6?ptc0, ptd7/t2ch1?ptd0/ss r pu 20 45 65 k capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf monitor mode entry voltage v tst v dd + 2.5 ? v dd + 4.0 v low-voltage inhibit, trip falling voltage v tripf 2.35 2.6 2.8 v low-voltage inhibit, trip rising voltage v tripr 2.4 2.66 2.9 v low-voltage inhibit reset/recover hysteresis (v tripf + v hys = v tripr ) v hys ?100 ?mv por rearm voltage (12) v por 0 ? 100 mv por reset voltage (13) v porrst 0 700 800 mv por rise time ramp rate (14) r por 0.02 ? ? v/ms 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t a (min) to t a (max), unless otherwise noted 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f osc = 16 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f osc = 16 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . measured with cgm and lvi enabled. 5. stop i dd is measured with osc1 = v ss . all inputs 0.2 v from rail. no dc loads . less than 100 pf on all outputs. all ports configured as inputs. typical values at midpoint of voltage range, 25c only. 6. stop i dd with tbm enabled is measured using an external square wave clock source (f osc = 4 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all inputs configured as inputs. 7. this parameter is characterized and not tested on each device. 8. all functional non-supply pins are internally clamped to v ss and v dd . 9. input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative cl amp voltages, then use the la rger of the two values. 10. power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consumin g power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 11. pullups and pulldowns are disabled. 12. maximum is highest voltage that por is guaranteed. 13. maximum is highest voltage that por is possible. 14. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. characteristic (1) symbol min typ (2) max unit 5.0-volt control timing mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 321 21.7 5.0-volt control timing 21.8 3.3-volt control timing figure 21-1. rst and irq timing characteristic (1) 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd unless otherwise noted. symbol min max unit frequency of operation crystal option external clock option (2) 2. no more than 10% duty cycle deviation from 50%. f osc 1 dc 8 32 mhz internal operating frequency f op (f bus ) ?8mhz internal clock period (1/f op )t cyc 125 ? ns reset input pulse width low t rl 100 ? ns irq interrupt pulse width low (edge-triggered) t ilih 100 ? ns irq interrupt pulse period (3) 3. the minimum period is the number of cycles it take s to execute the interrupt service routine plus 1 t cyc . t ilil note 3 ? t cyc characteristic (1) 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd unless otherwise noted. symbol min max unit frequency of operation crystal option external clock option (2) 2. no more than 10% duty cycle deviation from 50%. f osc 1 dc 8 16 mhz internal operating frequency f op (f bus ) ?4mhz internal clock period (1/f op )t cyc 250 ? ns reset input pulse width low t rl 200 ? ns irq interrupt pulse width low (edge-triggered) t ilih 200 ? ns irq interrupt pulse period (3) 3. the minimum period is the number of cycles it take s to execute the interrupt service routine plus 1 t cyc . t ilil note 3 ? t cyc rst irq t rl t ilih t ilil electrical specifications mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 322 freescale semiconductor 21.9 clock generation mo dule (cgm) characteristics 21.9.1 cgm oper ating conditions 21.9.2 cgm component information characteristic symbol min typ max unit operating voltage v dda v ssa v dd ? 0.3 v ss ? 0.3 ? ? v dd + 0.3 v ss + 0.3 v crystal reference frequency f rclk 1?8mhz input clock frequency (pll off) (1) 1. external square wave a pplied to osc1. voltage levels must be rail-to-rail and duty cycle must be 50%. f xclk ??32mhz range nominal multiplier f nom ? 71.42 ? khz vco center-of-range frequency (2) 2. range of frequencies that vco can produce to generate in put clock to frequency divider during acquisition and tracking modes. f vrs 71.42k ? 40m hz vco operating frequency (3) 3. allowed vco operating range. f vclk 71.42k ? 32m hz characteristic symbol min typ max unit crystal frequency f xclk 1?8mhz crystal load capacitance (1) 1. consult crystal manufa cturer?s specification. c l ?20?pf crystal fixed capacitance (2) 2. capacitor on osc1 pin. does not include para sitic capacitance due to package, pin, and board. c 1 ? (2 x c l ) ? 5 47 pf crystal tuning capacitance (3) 3. capacitor on osc2 pin. does not include para sitic capacitance due to package, pin, and board. c 2 ? (2 x c l ) ? 5 47 pf feedback bias resistor r b ?110m series damping resistor r s 00?k v dda /v ssa bypass capacitor c byp ?0.1? f cgmxfc filter values see table 4-5. example f ilter component values clock generation module (cgm) characteristics mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 323 21.9.3 cgm acquisiti on/lock time information characteristic symbol min typ max unit acquisition mode entry frequency tolerance (1) 1. deviation between vco frequency and desired frequency to enter pll acquisition mode. acq 3.6 ? 7.2 % tracking mode entry frequency tolerance (2) 2. deviation between vco frequency and desired frequency to enter pll tracking mode (stable). trk 0? 3.6 % lock entry frequency tolerance (3) 3. deviation between vco frequency and desired frequency to enter locked mode. lock 0? 0.9 % lock exit frequency tolerance (4) 4. deviation between vco frequency and desired frequency to exit locked mode. unl 0.9 ? 1.8 % reference cycles per acquisition mode period n acq ?32? reference cycles per tracking mode period n trk ? 128 ? automatic mode time to stable t acq n acq /f rclk see note (5) 5. acquisition time is an integer multiple of reference cycles divided by reference clock. ?s automatic stable to lock time t al n trk /f rclk see note (6) 6. stable to lock time is an integer multiple of reference cycles divided by reference clock. ?s automatic lock time (t acq + t al ) (7) 7. maximum lock time depends on cgmxfc f ilter components, power supply filtering, and reference clock stability. pll may not lock if improper components or po or filtering and layout are used. t lock ?525ms pll jitter, deviation of average bus frequency over 2 ms period f j 0? f rclk x 0.025% x n/4 hz electrical specifications mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 324 freescale semiconductor 21.10 5.0-volt adc characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, v ddad/ v refh = 5.0 vdc 10%, v ssad/ v refl = 0 vdc symbol min max unit comments supply voltage v ddad 4.5 5.5 v v ddad should be tied to the same potential as v dd via separate traces. input voltages v adin 0 v ddad v v adin <= v ddad resolution b ad 10 10 bits absolute accuracy a ad ?4 +4 lsb includes quantization adc internal clock f adic 500 k 1.048 m hz t aic = 1/f adic conversion range r ad v ssad v ddad v power-up time t adpu 16 ? t aic cycles conversion time t adc 16 17 t aic cycles sample time t ads 5? t aic cycles monotonicity m ad guaranteed zero inpu t reading z adi 000 003 hex v adin = v ssa full-scale reading f adi 3fc 3ff hex v adin = v dda input capacitance c adi ? 30 pf not tested v ddad /v refh current i vref ?1.6ma absolute accuracy (8-bit truncation mode) a ad ?1 + 1 lsb includes quantization quantization error (8-bit truncation mode) ? ?1/8 +7/8 lsb 3.3-volt adc characteristics mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 325 21.11 3.3-volt adc characteristics characteristic (1) 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, v ddad/ v refh = 3.3 vdc 10%, v ssad/ v refl = 0 vdc symbol min max unit comments supply voltage v ddad 3.0 3.6 v v ddad should be tied to the same potential as v dd via separate traces. input voltages v adin 0 v ddad v v adin <= v ddad resolution b ad 10 10 bits absolute accuracy a ad ?6 +6 lsb includes quantization adc internal clock f adic 500 k 1.048 m hz t aic = 1/f adic conversion range r ad v ssad v ddad v power-up time t adpu 16 ? t aic cycles conversion time t adc 16 17 t aic cycles sample time t ads 5? t aic cycles monotonicity m ad guaranteed zero inpu t reading z adi 000 005 hex v adin = v ssa full-scale reading f adi 3fa 3ff hex v adin = v dda input capacitance c adi ? 30 pf not tested v ddad /v refh current i vref ?1.2ma absolute accuracy (8-bit truncation mode) a ad ?1 + 1 lsb includes quantization quantization error (8-bit truncation mode) ? ?1/8 +7/8 lsb electrical specifications mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 326 freescale semiconductor 21.12 5.0-volt spi characteristics diagram number (1) 1. numbers refer to dimensions in figure 21-2 and figure 21-3 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc t cyc 2 enable lead time t lead(s) 1? t cyc 3 enable lag time t lag(s) 1? t cyc 4 clock (spsck) high time master slave t sckh(m) t sckh(s) t cyc ?25 1/2 t cyc ?25 64 t cyc ? ns ns 5 clock (spsck) low time master slave t sckl(m) t sckl(s) t cyc ?25 1/2 t cyc ?25 64 t cyc ? ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 30 30 ? ? ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 30 30 ? ? ns ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 40 40 ns ns 9 disable time, slave (4) 4. hold time to high-impedance state t dis(s) ?40ns 10 data valid time, after enable edge master slave (5) 5. with 100 pf on all spi pins t v(m) t v(s) ? ? 50 50 ns ns 11 data hold time, outputs, after enable edge master slave t ho(m) t ho(s) 0 0 ? ? ns ns 3.3-volt spi characteristics mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 327 21.13 3.3-volt spi characteristics diagram number (1) 1. numbers refer to dimensions in figure 21-2 and figure 21-3 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc t cyc 2 enable lead time t lead(s) 1? t cyc 3 enable lag time t lag(s) 1? t cyc 4 clock (spsck) high time master slave t sckh(m) t sckh(s) t cyc ?35 1/2 t cyc ?35 64 t cyc ? ns ns 5 clock (spsck) low time master slave t sckl(m) t sckl(s) t cyc ?35 1/2 t cyc ?35 64 t cyc ? ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 40 40 ? ? ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 40 40 ? ? ns ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 50 50 ns ns 9 disable time, slave (4) 4. hold time to high-impedance state t dis(s) ?50ns 10 data valid time, after enable edge master slave (5) 5. with 100 pf on all spi pins t v(m) t v(s) ? ? 60 60 ns ns 11 data hold time, outputs, after enable edge master slave t ho(m) t ho(s) 0 0 ? ? ns ns electrical specifications mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 328 freescale semiconductor figure 21-2. spi master timing note note: this first clock edge is generated internally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 11 10 11 7 6 note note: this last clock edge is generated inte rnally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) cpol = 0 cpol = 1 cpol = 0 cpol = 1 3.3-volt spi characteristics mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 329 figure 21-3. spi slave timing note: not defined but normally msb of character just received slave ss input spsck input spsck input miso input mosi output 4 5 5 1 4 msb in bits 6?1 8 6 10 5 11 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out note: not defined but normally lsb of character previ ously transmitted slave ss input spsck input spsck input miso output mosi input 4 5 5 1 4 msb in bits 6?1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11 cpol = 0 cpol = 1 cpol = 0 cpol = 1 electrical specifications mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 330 freescale semiconductor 21.14 timer interface module characteristics figure 21-4. timer input timing characteristic symbol min max unit timer input capture pulse width t th, t tl 2? t cyc timer input capture period t tltl note (1) 1. the minimum period is the number of cycles it take s to execute the interrupt service routine plus 1 t cyc . ? t cyc timer input clock pulse width t tcl , t tch t cyc + 5 ?ns input capture rising edge input capture falling edge input capture both edges t th t tl t tltl t tltl t tltl t tl t th tclk t tcl t tch memory characteristics mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 331 21.15 memory characteristics characteristic symbol min typ max unit ram data retention voltage v rdr 1.3 ? ? v flash program bus clock frequency ? 1 ? ? mhz flash read bus clock frequency f read (1) 1. f read is defined as the frequency range for which the flash memory can be read. 0?8 mhz flash page erase time <1 k cycles >1 k cycles t erase 0.9 3.6 1 4 1.1 5.5 ms flash mass erase time t merase 4??ms flash pgm/erase to hven setup time t nvs 10 ? ? s flash high-voltage hold time t nvh 5?? s flash high-voltage hold time (mass erase) t nvhl 100 ? ? s flash program hold time t pgs 5?? s flash program time t prog 30 ? 40 s flash return to read time t rcv (2) 2. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to 0. 1?? s flash cumulative program hv period t hv (3) 3. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x 32) t hv maximum. ?? 4ms flash endurance (4) 4. typical endurance was evaluated for this product family. for additional information on how freescale defines typical endurance , please refer to engineering bulletin eb619. ? 10 k 100 k ? cycles flash data retention time (5) 5. typical data retention values are based on intrinsic capability of the technology measured at high temp erature and de-rated to 25c using the arrhenius equation. for addi tional information on how freescale defines typical data retention , please refer to engineering bulletin eb618. ? 15 100 ? years electrical specifications mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 332 freescale semiconductor mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 333 chapter 22 ordering information and mechanical specifications 22.1 introduction this section contains ordering numbers for th e mc68hc908gz60 and gives the dimensions for: ? 32-pin low-profile quad flat pack (case 873a) ? 48-pin low-profile quad flat pack (case 932-03) ? 64-pin quad flat pack (case 840b) the following figures show the latest package drawings at the time of th is publication. to make sure that you have the latest package specifications, contact your local freescale sales office. 22.2 mc order numbers figure 22-1. device numbering system 22.3 package dimensions refer to the following pages fo r detailed package dimensions. table 22-1. mc order numbers mc order number operating temperature range package mc908gz60cfj ?40 c to +85 c 32-pin low-profile quad flat package (lqfp) mc908gz60vfj ?40 c to +105 c mc908gz60mfj ?40 c to +125 c mc908gz60cfa ?40 c to +85 c 48-pin low-profile quad flat package (lqfp) mc908gz60vfa ?40 c to +105 c mc908gz60mfa ?40 c to +125 c mc908gz60cfu ?40 c to +85 c 64-pin quad flat package (qfp) mc908gz60vfu ?40 c to +105 c mc908gz60mfu ?40 c to +125 c temperature designators: c = ?40c to +85c v = ?40c to +105c m = ?40c to +125c m c 9 0 8 g z 6 0 x xx e family package designator temperature range pb free mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 343 appendix a mc68hc908gz48 a.1 introduction the mc68hc908gz48 is a member of the low-co st, high-performance m68hc08 family of 8-bit microcontroller units (mcus). all mcus in the fa mily use the enhanced m68hc 08 central processor unit (cpu08) and are available with a variety of mo dules, memory sizes and types, and package types. the information contained in this document pertains to the mc68hc908gz48 with the exceptions shown in this appendix. a.2 block diagram see figure a-1 . a.3 memory the mc68hc908gz48 can address 48 kbytes of me mory space. the memory map, shown in figure a-2 , includes: ? 48 kbytes of user flash memory ? 1536 bytes of random-access memory (ram) ? 52 bytes of user-defined vectors mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 344 freescale semiconductor figure a-1. mc68hc908gz48 block diagram single breakpoint break module system integration module programmable timebase module monitor mode entry serial peripheral 6-channel timer interface module dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash ? 48,640 bytes user ram ? 1536 bytes monitor rom ? 304 bytes user flash vector space ? 52 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 rst (1) irq (1) interface module interrupt module computer operating properly module pta7/kbd7/ad15? 10-bit analog-to-digital converter module ptc6 (2) ptc5 (2) ptc4 (2, 3) ptc3 (2, 3) ptc2 (2, 3) ptc1/can rx (2, 3) ptc0/can tx (2, 3) ptd7/t2ch1 (2) ptd6/t2ch0 (2) ptd5/t1ch1 (2) ptd4/t1ch0 (2) ptd3/spsck (2) ptd2/mosi (2) ptd1/miso (2) ptd0/ss /mclk (2) pte1/rxd pte0/txd 2-channel timer interface module enhanced serial interface module security module power-on reset module memory map module configuration register 1?2 module power v ss v dd v ssa v dda 1. pin contains integrated pullup device. 2. ports are software configurable wi th pullup device if input port or pu llup/pulldown device for keyboard input. 3. higher current drive port pins v ddad /v refh v ssad /v refl pte5?pte2 communications clock generator module cgmxfc phase locked loop 1?8 mhz oscillator portb ddrb ptb7/ad7? portf ddrf ptf7/t2ch5 module portg ddrg ptg7/ad23? ptf6/t2ch4 ptf5/t2ch3 ptf4/t2ch2 ptf3?pft0 (3) mscan module pta0/kbd0/ad8 (2) ptb0/ad0 ptg0/ad16 mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 345 $0000 $003f i/o registers 64 bytes $fe00 sim break status register (bsr) $fe01 sim reset status register (srsr) $fe02 reserved $0040 $043f ram-1 1024 bytes $fe03 sim break flag co ntrol register (bfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $0440 $0461 i/o registers 34 bytes $fe06 interrupt status register 3 (int3) $fe07 interrupt status register 4 (int4) $fe08 flash-2 control register (fl2cr) $0462 $04ff reserved $fe09 break address register high (brkh) $fe0a break address register low (brkl) $fe0b break status and control register (brkscr) $0500 $057f mscan control and message buffer 128 bytes $fe0c lvi status register (lvisr) $fe0d flash-2 test cont rol register (fltcr2) $fe0e flash-1 test cont rol register (fltcr1) $0580 $077f ram-2 512 bytes $fe0f unimplemented $fe10 $fe1f unimplemented 16 bytes reserved for compatibil ity with monitor code for a-family part $0780 $1dff reserved $fe20 $ff7f monitor rom 352 bytes $1e00 $1e0f monitor rom 16 bytes $ff80 flash-1 block prot ect register (fl1bpr) $ff81 flash-2 block prot ect register (fl2bpr) $1e10 $3fff reserved $ff82 $ff87 reserved $4000 $7fff flash-2 16,384 bytes $ff88 flash-1 control register (fl1cr) $ff89 $ffcb reserved $8000 $fdff flash-1 32,256 bytes $ffcc $ffff (1) flash-1 vectors 52 bytes 1. $fff6?$fffd used for eight security bytes figure a-2. mc68hc908gz48 memory map mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 346 freescale semiconductor a.4 ordering information figure a-3. device numbering system table a-1. mc order numbers mc order number operating temperature range package mc908gz48cfj ?40 c to +85 c 32-pin low-profile quad flat package (lqfp) mc908gz48vfj ?40 c to +105 c mc908gz48mfj ?40 c to +125 c mc908gz48cfa ?40 c to +85 c 48-pin low-profile quad flat package (lqfp) mc908gz48vfa ?40 c to +105 c mc908gz48mfa ?40 c to +125 c mc908gz48cfu ?40 c to +85 c 64-pin quad flat package (qfp) mc908gz48vfu ?40 c to +105 c mc908gz48mfu ?40 c to +125 c temperature designators: c = ?40c to +85c v = ?40c to +105c m = ?40c to +125c m c 9 0 8 g z 4 8 x xx e family package designator temperature range pb free mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 347 appendix b mc68hc908gz32 b.1 introduction the mc68hc908gz32 is a member of the low-co st, high-performance m68hc08 family of 8-bit microcontroller units (mcus). all mcus in the fa mily use the enhanced m68hc 08 central processor unit (cpu08) and are available with a variety of mo dules, memory sizes and types, and package types. the information contained in this document pertains to the mc68hc908gz32 with the exceptions shown in this appendix. b.2 block diagram see figure b-1 . b.3 memory the mc68hc908gz32 can address 32 kbytes of me mory space. the memory map, shown in figure b-2 , includes: ? 32 kbytes of user flash memory ? 1536 bytes of random-access memory (ram) ? 52 bytes of user-defined vectors mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 348 freescale semiconductor figure b-1. mc68hc908gz32 block diagram single breakpoint break module system integration module programmable timebase module monitor mode entry serial peripheral 6-channel timer interface module dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash ? 32,256 bytes user ram ? 1536 bytes monitor rom ? 304 bytes user flash vector space ? 52 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 rst (1) irq (1) interface module interrupt module computer operating properly module pta7/kbd7/ad15? 10-bit analog-to-digital converter module ptc6 (2) ptc5 (2) ptc4 (2, 3) ptc3 (2, 3) ptc2 (2, 3) ptc1/can rx (2, 3) ptc0/can tx (2, 3) ptd7/t2ch1 (2) ptd6/t2ch0 (2) ptd5/t1ch1 (2) ptd4/t1ch0 (2) ptd3/spsck (2) ptd2/mosi (2) ptd1/miso (2) ptd0/ss /mclk (2) pte1/rxd pte0/txd 2-channel timer interface module enhanced serial interface module security module power-on reset module memory map module configuration register 1?2 module power v ss v dd v ssa v dda 1. pin contains integrated pullup device. 2. ports are software configurable wi th pullup device if input port or pu llup/pulldown device for keyboard input. 3. higher current drive port pins v ddad /v refh v ssad /v refl pte5?pte2 communications clock generator module cgmxfc phase locked loop 1?8 mhz oscillator portb ddrb ptb7/ad7? portf ddrf ptf7/t2ch5 module portg ddrg ptg7/ad23? ptf6/t2ch4 ptf5/t2ch3 ptf4/t2ch2 ptf3?pft0 (3) mscan module ptb0/ad0 ptg0/ad16 pta0/kbd0/ad8 (2) mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 freescale semiconductor 349 $0000 $003f i/o registers 64 bytes $fe00 sim break status register (bsr) $fe01 sim reset status register (srsr) $fe02 reserved $0040 $043f ram-1 1024 bytes $fe03 sim break flag co ntrol register (bfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $0440 $0461 i/o registers 34 bytes $fe06 interrupt status register 3 (int3) $fe07 interrupt status register 4 (int4) $fe08 unimplemented $0462 $04ff reserved $fe09 break address register high (brkh) $fe0a break address register low (brkl) $fe0b break status and control register (brkscr) $0500 $057f mscan control and message buffer 128 bytes $fe0c lvi status register (lvisr) $fe0d unimplemented $fe0e flash-1 test cont rol register (fltcr1) $0580 $077f ram-2 512 bytes $fe0f unimplemented $fe10 $fe1f unimplemented 16 bytes reserved for compatibil ity with monitor code for a-family part $0780 $1dff reserved $fe20 $ff7f monitor rom 352 bytes $1e00 $1e0f monitor rom 16 bytes $ff80 flash-1 block prot ect register (fl1bpr) $ff81 $ff87 reserved $1e10 $7fff reserved $ff88 flash-1 control register (fl1cr) $ff89 $ffcb reserved $8000 $fdff flash-1 32,256 bytes $ffcc $ffff (1) flash-1 vectors 52 bytes 1. $fff6?$fffd used for eight security bytes figure b-2. mc68hc908gz32 memory map mc68hc908gz60 ? mc68hc908gz48 ? mc68hc908gz32 data sheet, rev. 6 350 freescale semiconductor b.4 ordering information figure b-3. device numbering system table b-1. mc order numbers mc order number operating temperature range package mc908gz32cfj ?40 c to +85 c 32-pin low-profile quad flat package (lqfp) mc908gz32vfj ?40 c to +105 c mc908gz32mfj ?40 c to +125 c mc908gz32cfa ?40 c to +85 c 48-pin low-profile quad flat package (lqfp) mc908gz32vfa ?40 c to +105 c mc908gz32mfa ?40 c to +125 c mc908gz32cfu ?40 c to +85 c 64-pin quad flat package (qfp) mc908gz32vfu ?40 c to +105 c mc908gz32mfu ?40 c to +125 c temperature designators: c = ?40c to +85c v = ?40c to +105c m = ?40c to +125c m c 9 0 8 g z 3 2 x xx e family package designator temperature range pb free how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data shee ts and/or specificati ons can and do vary in different applications and actual perfo rmance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2005, 2006, 2007. all rights reserved. mc68hc908gz60 rev. 6, 04/2007 |
Price & Availability of MC908GZ60CFUE
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |